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Searched refs:regclass (Results 1 – 16 of 16) sorted by relevance

/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1765 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1766 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1771 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1772 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1775 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
1777 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1778 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1782 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1783 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1784 regclass:$dst4),
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DNVPTXVector.td239 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
241 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a, regclass:$b),
243 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
253 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
255 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a),
257 [(set regclass:$dst, (OpNode regclass:$a))], sInst>;
493 multiclass VMADV2Only<string asmstr, NVPTXRegClass regclass, NVPTXInst sop=NOP,
495 def V2 : NVPTXVecInst<(outs regclass:$dst),
496 (ins regclass:$a, regclass:$b, regclass:$c),
498 [(set regclass:$dst, (add
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DNVPTXIntrinsics.td838 multiclass F_ATOMIC_2_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
841 def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
847 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
849 def imm : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, IMMType:$b),
855 [(set regclass:$dst, (IntOp ptrclass:$addr, IMM:$b))]>,
858 multiclass F_ATOMIC_2<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
860 defm p32 : F_ATOMIC_2_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
862 defm p64 : F_ATOMIC_2_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
867 multiclass F_ATOMIC_2_NEG_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
870 def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
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/external/libunwind_llvm/src/
DUnwind-EHABI.cpp789 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Set() argument
794 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Set()
798 switch (regclass) { in _Unwind_VRS_Set()
842 _Unwind_VRS_RegClass regclass, uint32_t regno, in _Unwind_VRS_Get_Internal() argument
846 switch (regclass) { in _Unwind_VRS_Get_Internal()
890 _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Get() argument
895 _Unwind_VRS_Get_Internal(context, regclass, regno, representation, in _Unwind_VRS_Get()
899 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Get()
906 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Pop() argument
911 static_cast<void *>(context), regclass, discriminator, in _Unwind_VRS_Pop()
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/external/libunwind_llvm/include/
Dunwind.h192 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
197 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
202 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
/external/llvm/test/CodeGen/PowerPC/
Dvariable_elem_vec_extracts.ll100 ; FIXME: the instruction below is a redundant regclass copy, to be removed
106 ; FIXME: the instruction below is a redundant regclass copy, to be removed
112 ; FIXME: the instruction below is a redundant regclass copy, to be removed
/external/llvm/test/CodeGen/X86/
Dcoalescer-subreg.ll2 ; This used to crash when coalescing a regclass like GR16 which did not support
Dh-registers-0.ll14 ; See FIXME: on regclass GR8.
/external/llvm/test/CodeGen/ARM/
Dvldlane.ll503 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
504 ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
/external/llvm/include/llvm/Target/
DTarget.td548 /// type that it doesn't know, and resolves the actual regclass to use by using
642 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
645 RegisterClass RegClass = regclass;
826 let InOperandList = (ins unknown:$src, i32imm:$regclass);
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td550 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
565 RegisterClass RegClass = regclass;
672 // both a regclass and EFLAGS as a result.
681 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
/external/llvm/test/CodeGen/AMDGPU/
Dsgpr-copy.ll228 ; registers were being identified as an SGPR regclass which was causing
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td204 // Condition code regclass.
DAArch64InstrFormats.td584 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
588 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
606 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
610 let MIOperandInfo = (ops regclass, shiftop);
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td1326 // can be SP. We need another regclass (similar to rGPR) to represent
DARMInstrInfo.td2223 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.