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Searched refs:stencil_tile_split (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_winsys.h207 unsigned *stencil_tile_split,
227 unsigned stencil_tile_split,
Dradeon_drm_bo.c715 unsigned *stencil_tile_split, in radeon_bo_get_tiling() argument
737 if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) { in radeon_bo_get_tiling()
741 …*stencil_tile_split = (args.tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TI… in radeon_bo_get_tiling()
753 unsigned stencil_tile_split, in radeon_bo_set_tiling() argument
790 args.tiling_flags |= (stencil_tile_split & in radeon_bo_set_tiling()
/external/libdrm/radeon/
Dradeon_surface.h134 uint32_t stencil_tile_split; member
Dradeon_surface.c822 surf->stencil_tile_split, surf->bo_size, 0); in eg_surface_init_2d_miptrees()
958 surf->stencil_tile_split = 64; in eg_surface_best()
968 surf->stencil_tile_split = surf_man->hw_info.row_size / 2; in eg_surface_best()
1317 surf->stencil_tile_split = 64; in si_surface_sanity()
1341 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split); in si_surface_sanity()
1712 …->stencil_level, 1, stencil_tile_mode, num_pipes, num_banks, surf->stencil_tile_split, surf->bo_si… in si_surface_init_2d_miptrees()
2145 surf->stencil_tile_split = 64; in cik_surface_sanity()
2171 &surf->stencil_tile_split, in cik_surface_sanity()
2315 surf->stencil_tile_split, num_pipes, num_banks, in cik_surface_init_2d_miptrees()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dr600_texture.c236 surface->stencil_tile_split, in r600_texture_get_handle()
609 &surface.stencil_tile_split, in si_texture_from_handle()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_texture.c222 surface->stencil_tile_split, in r600_texture_get_handle()
542 &surface.stencil_tile_split, in r600_texture_from_handle()
Devergreen_state.c1494 unsigned i, stile_split = rtex->surface.stencil_tile_split; in evergreen_init_depth_surface()