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Searched refs:COND (Results 1 – 22 of 22) sorted by relevance

/toolchain/binutils/binutils-2.25/opcodes/
Darc-opc.c239 #define COND (DELAY + 1) macro
243 #define FORCELIMM (COND + 1)
1501 { "al", 0, COND, 0 },
1502 { "ra", 0, COND, 0 },
1503 { "eq", 1, COND, 0 },
1504 { "z", 1, COND, 0 },
1505 { "ne", 2, COND, 0 },
1506 { "nz", 2, COND, 0 },
1507 { "pl", 3, COND, 0 },
1508 { "p", 3, COND, 0 },
[all …]
Dfrv-opc.c1645 …{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0…
1651 …{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0…
1657 …{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0…
1663 …{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0…
1669 …{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0…
1675 { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
1681 …OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } },
1687 …{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0…
1693 …{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0…
1699 …{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0…
[all …]
Dsparc-opc.c110 #define COND(x) (((x) & 0xf) << 25) macro
121 #define CONDA (COND (0x8))
122 #define CONDCC (COND (0xd))
123 #define CONDCS (COND (0x5))
124 #define CONDE (COND (0x1))
125 #define CONDG (COND (0xa))
126 #define CONDGE (COND (0xb))
127 #define CONDGU (COND (0xc))
128 #define CONDL (COND (0x3))
129 #define CONDLE (COND (0x2))
[all …]
Drl78-decode.opc127 #define COND(c) rl78->op[1].condition = RL78_Condition_##c
333 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
336 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
339 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
342 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH);
345 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z);
348 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ);
353 ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
356 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F);
359 ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
[all …]
Drl78-decode.c128 #define COND(c) rl78->op[1].condition = RL78_Condition_##c macro
843 ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); in rl78_decode_opcode()
863 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); in rl78_decode_opcode()
881 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); in rl78_decode_opcode()
901 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); in rl78_decode_opcode()
919 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F); in rl78_decode_opcode()
939 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F); in rl78_decode_opcode()
1129 ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T); in rl78_decode_opcode()
1147 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T); in rl78_decode_opcode()
1165 ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T); in rl78_decode_opcode()
[all …]
Dxc16x-opc.c1973 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
1979 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
1985 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
1991 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
1997 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
2003 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
2009 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
2015 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
2021 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
2027 { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
[all …]
Daarch64-tbl.h1787 …{"ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM…
1788 …{"ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM…
1790 {"ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
1791 {"ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
1793 {"csel", 0x1a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF},
1794 …{"csinc", 0x1a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS |…
1797 …{"csinv", 0x5a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS |…
1800 …{"csneg", 0x5a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS |…
1897 {"fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
1898 …{"fccmpe", 0x1e200410, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
[all …]
DChangeLog-2013131 COND for cinc, cset, cinv, csetm and cneg.
DChangeLog-989921 (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s
/toolchain/binutils/binutils-2.25/binutils/
Dsysinfo.y44 %token COND
222 cond_it_field: '(' COND NAME
Dsyslex.l84 "cond" { return COND;}
/toolchain/binutils/binutils-2.25/cpu/
Diq2000m.cpu125 (dni bctxt "branch and switch context" (MACH2000 DELAY-SLOT COND-CTI USES-RS)
131 (dni bc0f "branch if copro 0 condition false" (MACH2000 DELAY-SLOT COND-CTI)
137 (dni bc0fl "branch if copro 0 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
143 (dni bc3f "branch if copro 3 condition false" (MACH2000 DELAY-SLOT COND-CTI)
149 (dni bc3fl "branch if copro 3 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
155 (dni bc0t "branch if copro 0 condition true" (MACH2000 DELAY-SLOT COND-CTI)
161 (dni bc0tl "branch if copro 0 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
167 (dni bc3t "branch if copro 3 condition true" (MACH2000 DELAY-SLOT COND-CTI)
173 (dni bc3tl "branch if copro 3 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
Dm32r.cpu884 (COND-CTI (PIPE O) (IDOC BR))
894 (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
900 (COND-CTI (IDOC BR))
910 (COND-CTI RELAXED (IDOC BR))
916 (COND-CTI (IDOC BR))
926 (dni sym comment (COND-CTI (IDOC BR))
980 (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
994 (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
1000 (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
1012 (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
[all …]
Dor1korbis.cpu398 (!COND-CTI UNCOND-CTI)
409 (!COND-CTI UNCOND-CTI)
423 (!COND-CTI UNCOND-CTI)
434 (!COND-CTI UNCOND-CTI)
448 (COND-CTI !UNCOND-CTI)
459 (COND-CTI !UNCOND-CTI)
Depiphany.cpu1098 ;; B<COND> SIMM8
1099 ;; B<COND> SIMM24
1106 (COND-CTI SHORT-INSN)
1116 (COND-CTI RELAXABLE)
1123 (COND-CTI)
1133 (COND-CTI RELAXED)
1776 ;; MOV<COND> RD,RN
Dxc16x.cpu1871 (COND-CTI (PIPE OS) (IDOC JMP))
1888 (COND-CTI (PIPE OS) (IDOC JMP))
1902 (COND-CTI (PIPE OS) (IDOC JMP))
2105 (COND-CTI (PIPE OS) (IDOC JMP))
2120 (COND-CTI (PIPE OS) (IDOC JMP))
2138 ( COND-CTI (PIPE OS) (IDOC JMP))
Dcris.cpu1182 "dsh bit for MACH-V32, with bit only changeable when X-COND"
2935 ; generic PRE-V32 movem; possibly related to then being a COND-CTI rather
/toolchain/binutils/binutils-2.25/gas/doc/
Dc-vax.texi236 @item j@var{COND}
237 @var{COND} may be any one of the conditional branches
241 @var{COND} may also be one of the bit tests
244 @var{NOTCOND} is the opposite condition to @var{COND}.
247 @kbd{b@var{COND} @dots{}}
/toolchain/binutils/binutils-2.25/bfd/
Delf-eh-frame.c463 #define REQUIRE(COND) \ in _bfd_elf_parse_eh_frame() argument
465 if (!(COND)) \ in _bfd_elf_parse_eh_frame()
Delfxx-sparc.c4054 #define COND(x) (((x)&0xf)<<25) in _bfd_sparc_elf_relocate_section() macro
4055 #define CONDA COND(0x8) in _bfd_sparc_elf_relocate_section()
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-sparc.c3406 #define COND(x) (((x)&0xf)<<25) in md_apply_fix() macro
3407 #define CONDA COND(0x8) in md_apply_fix()
Dtc-arm.c18861 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18862 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18863 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18864 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18865 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18866 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18867 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18868 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18869 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18870 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
[all …]