| /toolchain/binutils/binutils-2.25/gas/doc/ |
| D | c-pdp11.texi | 29 The PDP-11 version of @code{@value{AS}} has a rich set of machine
34 @table @code
38 Generate position-independent (or position-dependent) code.
40 The default is to generate position-independent code.
47 Most options come in two variants: a @code{-m}@var{extension} that
48 enables @var{extension}, and a @code{-mno-}@var{extension} that disables
53 @table @code
67 consists of these instructions: @code{ADDNI}, @code{ADDN}, @code{ADDPI},
68 @code{ADDP}, @code{ASHNI}, @code{ASHN}, @code{ASHPI}, @code{ASHP},
69 @code{CMPCI}, @code{CMPC}, @code{CMPNI}, @code{CMPN}, @code{CMPPI},
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| D | c-arm.texi | 33 @table @code
35 @cindex @code{-mcpu=} command line option, ARM
41 @code{arm1},
42 @code{arm2},
43 @code{arm250},
44 @code{arm3},
45 @code{arm6},
46 @code{arm60},
47 @code{arm600},
48 @code{arm610},
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| D | c-nios2.texi | 34 @cindex @code{relax-section} command line option, Nios II
36 Replace identified out-of-range branches with PC-relative @code{jmp}
37 sequences when possible. The generated code sequences are suitable
38 for use in position-independent code, but there is a practical limit
42 @cindex @code{relax-all} command line option, Nios II
45 and all call instructions with @code{jmp} and @code{callr} sequences
47 target symbols and is not appropriate for position-independent code.
49 @cindex @code{no-relax} command line option, Nios II
53 @cindex @code{EB} command line option, Nios II
57 @cindex @code{EL} command line option, Nios II
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| D | c-tic54x.texi | 36 The TMS320C54X version of @code{@value{AS}} has a few machine-dependent options.
43 @samp{.far_mode} directive in the assembly code. If you do not use the
50 assembly code. For recognized CPU codes, see
51 @xref{TIC54X-Directives,,@code{.version}}. The default CPU version is
82 The TIC54X version of @code{@value{AS}} allows the following additional
87 Binary @code{000000B, 011000b}
88 Octal @code{10Q, 224q}
89 Hexadecimal @code{45h, 0FH}
97 #define macros. When @code{@value{AS}} encounters one of these
101 Subsyms may be defined using the @code{.asg} and @code{.eval} directives
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| D | c-v850.texi | 21 @code{@value{AS}} supports the following additional command-line options
26 @table @code
28 @cindex @code{-wsigned_overflow} command line option, V850
35 @cindex @code{-wunsigned_overflow} command line option, V850
42 @cindex @code{-mv850} command line option, V850
44 Specifies that the assembled code should be marked as being targeted at
46 such code with code assembled for other processors.
48 @cindex @code{-mv850e} command line option, V850
50 Specifies that the assembled code should be marked as being targeted at
52 such code with code assembled for other processors.
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| D | c-alpha.texi | 33 @code{@value{AS}} also supports the ECOFF and EVAX formats, but
43 @cindex @code{-m@var{cpu}} command line option, Alpha
48 error message. This option is equivalent to the @code{.arch} directive.
51 @code{21064},
52 @code{21064a},
53 @code{21066},
54 @code{21068},
55 @code{21164},
56 @code{21164a},
57 @code{21164pc},
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| D | c-tic6x.texi | 31 @cindex @code{-march=} command line option, TIC6X
36 The following values of @var{arch} are accepted: @code{c62x},
37 @code{c64x}, @code{c64x+}, @code{c67x}, @code{c67x+}, @code{c674x}.
39 @cindex @code{-mdsbt} command line option, TIC6X
40 @cindex @code{-mno-dsbt} command line option, TIC6X
44 @code{Tag_ABI_DSBT} attribute with a value of 1, indicating that the
45 code is using DSBT addressing. The @option{-mno-dsbt} option, the
46 default, causes the tag to have a value of 0, indicating that the code
50 @cindex @code{-mpid=} command line option, TIC6X
55 @code{Tag_ABI_PID} attribute with a value indicating the form of data
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| D | c-ppc.texi | 49 Generate code for POWER/2 (RIOS2).
52 Generate code for POWER (RIOS1)
55 Generate code for PowerPC 601.
58 Generate code for PowerPC 603/604.
61 Generate code for PowerPC 403/405.
64 Generate code for PowerPC 440. BookE and some 405 instructions.
67 Generate code for PowerPC 464.
70 Generate code for PowerPC 476.
73 Generate code for PowerPC 7400/7410/7450/7455.
76 Generate code for PowerPC 750CL.
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| D | c-xtensa.texi | 46 @code{L32R} instructions in the text section. These options only affect
47 literals referenced via PC-relative @code{L32R} instructions; literals
48 for absolute mode @code{L32R} instructions are handled separately.
54 Indicate to the assembler whether @code{L32R} instructions use absolute
56 addressing option, the default is to use absolute @code{L32R}
57 relocations. Otherwise, only the PC-relative @code{L32R} relocations
64 expense in code size. @xref{Xtensa Automatic Alignment, ,Automatic
66 that the assembler will always align instructions like @code{LOOP} that
75 targets can potentially be out of range. It may degrade both code size
102 does not affect code size or performance. The default is
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| D | c-mips.texi | 15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
28 * MIPS assembly options:: Directives to control code generation
43 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
46 @table @code
47 @cindex @code{-G} option (MIPS)
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
60 Any MIPS configuration of @code{@value{AS}} can select big-endian or
93 Generate code for a particular MIPS Instruction Set Architecture level.
114 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
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| D | c-vax.texi | 35 The Vax version of @code{@value{AS}} accepts any of the following options,
40 @table @code
41 @cindex @code{-D}, ignored on VAX
42 @cindex @code{-S}, ignored on VAX
43 @cindex @code{-T}, ignored on VAX
44 @item @code{-D} (Debug)
45 @itemx @code{-S} (Symbol Table)
46 @itemx @code{-T} (Token Trace)
49 @cindex @code{-d}, VAX option
50 @item @code{-d} (Displacement size for JUMPs)
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| D | c-i386.texi | 20 The i386 version @code{@value{AS}} supports both the original Intel 386
52 The i386 version of @code{@value{AS}} has a few machine
76 alignment within code sections with multi-byte nop instructions such
94 @code{i8086},
95 @code{i186},
96 @code{i286},
97 @code{i386},
98 @code{i486},
99 @code{i586},
100 @code{i686},
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| /toolchain/binutils/binutils-2.25/bfd/ |
| D | elf-m10200.c | 181 bfd_reloc_code_real_type code) in bfd_elf32_bfd_reloc_type_lookup() argument
189 if (mn10200_reloc_map[i].bfd_reloc_val == code) in bfd_elf32_bfd_reloc_type_lookup()
696 unsigned char code; in mn10200_elf_relax_section() local
699 code = bfd_get_8 (abfd, contents + irel->r_offset - 1); in mn10200_elf_relax_section()
701 if (code != 0xe0 && code != 0xe1) in mn10200_elf_relax_section()
710 if (code == 0xe0) in mn10200_elf_relax_section()
712 else if (code == 0xe1) in mn10200_elf_relax_section()
749 unsigned char code; in mn10200_elf_relax_section() local
752 code = bfd_get_8 (abfd, contents + irel->r_offset - 1); in mn10200_elf_relax_section()
754 if (code != 0xfc) in mn10200_elf_relax_section()
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| D | cpu-ia64-opc.c | 36 ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED) in ins_rsvd()
43 ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED) in ext_rsvd()
50 ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED) in ins_const()
57 ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED) in ext_const()
63 ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) in ins_reg() argument
68 *code |= value << self->field[0].shift; in ins_reg()
73 ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) in ext_reg() argument
75 *valuep = ((code >> self->field[0].shift) in ext_reg()
81 ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) in ins_immu() argument
95 *code |= new_insn; in ins_immu()
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| D | elf32-ip2k.c | 51 #define IS_PAGE_OPCODE(code) \ argument
52 ip2k_is_opcode (code, ip2k_page_opcode)
60 #define IS_JMP_OPCODE(code) \ argument
61 ip2k_is_opcode (code, ip2k_jmp_opcode)
69 #define IS_SNC_OPCODE(code) \ argument
70 ip2k_is_opcode (code, ip2k_snc_opcode)
78 #define IS_INC_1SP_OPCODE(code) \ argument
79 ip2k_is_opcode (code, ip2k_inc_1sp_opcode)
87 #define IS_ADD_2SP_W_OPCODE(code) \ argument
88 ip2k_is_opcode (code, ip2k_add_2sp_w_opcode)
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| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | aarch64-asm-2.c | 350 aarch64_insn *code, const aarch64_inst *inst) in aarch64_insert_operand() argument
381 return aarch64_ins_regno (self, info, code, inst); in aarch64_insert_operand()
383 return aarch64_ins_reg_extended (self, info, code, inst); in aarch64_insert_operand()
385 return aarch64_ins_reg_shifted (self, info, code, inst); in aarch64_insert_operand()
387 return aarch64_ins_ft (self, info, code, inst); in aarch64_insert_operand()
391 return aarch64_ins_reglane (self, info, code, inst); in aarch64_insert_operand()
393 return aarch64_ins_reglist (self, info, code, inst); in aarch64_insert_operand()
395 return aarch64_ins_ldst_reglist (self, info, code, inst); in aarch64_insert_operand()
397 return aarch64_ins_ldst_reglist_r (self, info, code, inst); in aarch64_insert_operand()
399 return aarch64_ins_ldst_elemlist (self, info, code, inst); in aarch64_insert_operand()
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| D | aarch64-asm.c | 38 insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...) in insert_fields() argument
52 insert_field (kind, code, value, mask); in insert_fields()
63 aarch64_insn *code, in aarch64_ins_regno() argument
66 insert_field (self->fields[0], code, info->reg.regno, 0); in aarch64_ins_regno()
75 aarch64_insn *code, const aarch64_inst *inst) in aarch64_ins_reglane() argument
78 insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask); in aarch64_ins_reglane()
89 insert_field (FLD_imm4, code, value, 0); in aarch64_ins_reglane()
101 insert_field (FLD_imm5, code, value, 0); in aarch64_ins_reglane()
112 insert_fields (code, info->reglane.index, 0, 3, FLD_M, FLD_L, FLD_H); in aarch64_ins_reglane()
116 insert_fields (code, info->reglane.index, 0, 2, FLD_L, FLD_H); in aarch64_ins_reglane()
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| D | m68hc11-dis.c | 239 unsigned int code; in print_insn() local
253 code = (buffer[0] << 8) + buffer[1]; in print_insn()
260 if ((opcode->opcode != (code & opcode->xg_mask)) || (opcode->arch != cpuxgate)) in print_insn()
270 (*info->fprintf_func) (info->stream, " #0x%x", (code >> 8) & 0x7); in print_insn()
273 (code >> 8) & 0x7, (code >> 5) & 0x7); in print_insn()
276 (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7); in print_insn()
279 (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7); in print_insn()
282 (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7); in print_insn()
285 (code >> 8) & 0x7, (code >> 5) & 0x7, (code >> 2) & 0x7); in print_insn()
288 (code >> 8) & 0x7, (code >> 5) & 0x7, code & 0x1f); in print_insn()
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| /toolchain/binutils/binutils-2.25/libiberty/ |
| D | pexecute.txh | 11 @table @code
30 temporary files; it may be @code{NULL} to use a randomly chosen name.
39 @code{NULL}. On failure it returns an error message, a statically
42 @var{obj} is returned by a previous call to @code{pex_init}.
46 @table @code
53 @code{NULL}, to the standard output of the calling program. Do @emph{not}
54 set this bit if you want to call @code{pex_read_output}
55 (described below). After a call to @code{pex_run} with this bit set,
81 @code{pex_run} using @code{PEX_BINARY_OUTPUT} should be followed by a
82 call using @code{PEX_BINARY_INPUT}.
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| D | simple-object.txh | 7 @code{simple_object_read} pointer which may be passed to other
12 @var{offset} is the offset into the file; this will be @code{0} in the
21 If an error occurs, this functions returns @code{NULL} and sets
22 @code{*@var{errmsg}} to an error string and sets @code{*@var{err}} to
23 an errno value or @code{0} if there is no relevant errno.
36 @code{simple_object_open_read}. The @var{data} argument to this
39 If @var{pfn} returns @code{0}, the loop over the sections stops and
40 @code{simple_object_find_sections} returns. If @var{pfn} returns some
43 On success @code{simple_object_find_sections} returns. On error it
44 returns an error string, and sets @code{*@var{err}} to an errno value
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| D | functions.texi | 12 calls to this function. Memory is allocated using @code{xmalloc} under
16 GNU Autoconf test @code{AC_FUNC_ALLOCA} to test for and properly make
17 available this function. The @code{AC_FUNC_ALLOCA} test requires that
18 client code use a block of preprocessor code to be safe (see the Autoconf
27 Like @code{sprintf}, but instead of passing a pointer to a buffer, you
29 the buffer needed, allocate memory with @code{malloc}, and store a
30 pointer to the allocated memory in @code{*@var{resptr}}. The value
31 returned is the same as @code{sprintf} would return. If memory could
32 not be allocated, minus one is returned and @code{NULL} is stored in
33 @code{*@var{resptr}}.
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| /toolchain/binutils/binutils-2.25/binutils/ |
| D | unwind-ia64.c | 176 #define UNW_DEC_BAD_CODE(code) \ argument
177 printf ("Unknown code 0x%02x\n", code)
590 unw_decode_x1 (const unsigned char *dp, unsigned int code ATTRIBUTE_UNUSED, in unw_decode_x1()
608 unw_decode_x2 (const unsigned char *dp, unsigned int code ATTRIBUTE_UNUSED, in unw_decode_x2()
628 unw_decode_x3 (const unsigned char *dp, unsigned int code ATTRIBUTE_UNUSED, in unw_decode_x3()
650 unw_decode_x4 (const unsigned char *dp, unsigned int code ATTRIBUTE_UNUSED, in unw_decode_x4()
674 unw_decode_r1 (const unsigned char *dp, unsigned int code, void *arg) in unw_decode_r1() argument
676 int body = (code & 0x20) != 0; in unw_decode_r1()
679 rlen = (code & 0x1f); in unw_decode_r1()
685 unw_decode_r2 (const unsigned char *dp, unsigned int code, void *arg) in unw_decode_r2() argument
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| /toolchain/binutils/binutils-2.25/gold/ |
| D | aarch64-reloc-property.h | 82 code() const in code() function
135 AArch64_reloc_property(unsigned int code, const char* name, Reloc_type rtype,
186 get_reloc_property(unsigned int code) const in get_reloc_property() argument
188 unsigned int idx = code_to_array_index(code); in get_reloc_property()
195 get_implemented_static_reloc_property(unsigned int code) const in get_implemented_static_reloc_property() argument
197 unsigned int idx = code_to_array_index(code); in get_implemented_static_reloc_property()
209 reloc_name_in_error_message(unsigned int code);
220 code_to_array_index(unsigned int code) const in code_to_array_index() argument
222 if (code == 0) return 0; in code_to_array_index()
223 if (!((code >= elfcpp::R_AARCH64_ABS64 && in code_to_array_index()
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| /toolchain/binutils/binutils-2.25/gas/config/ |
| D | tc-pdp11.c | 34 int code; member
238 valueT code; in md_apply_fix() local
247 code = md_chars_to_number ((unsigned char *) buf, size); in md_apply_fix()
273 code &= ~mask; in md_apply_fix()
274 code |= (val >> shift) & mask; in md_apply_fix()
275 number_to_chars_littleendian (buf, code, size); in md_apply_fix()
334 operand->code = *str - '0'; in parse_reg()
345 operand->code = 6; in parse_reg()
351 operand->code = 7; in parse_reg()
377 operand->code = *str - '0'; in parse_ac5()
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| /toolchain/binutils/binutils-2.25/ld/ |
| D | ldint.texinfo | 73 This file documents the internals of the GNU linker @code{ld}. It is a
76 GNU @code{ld} as you discover it (or as you design changes to @code{ld}).
120 script will create the emulation source file, which contains C code.
121 This C code permits the linker emulation to override various linker
122 behaviours. Most targets use the generic emulation code, which is in
133 @file{scripttempl/aout.sc}, and creates the emulation code using
138 the @code{-m} option. The @code{-V} option will list all supported
151 by setting the shell variable @code{targ_emul} in @file{configure.tgt}.
155 Certain conventions are enforced. Suppose the @code{targ_emul} variable
161 directories. The @file{Makefile} target must invoke @code{GENSCRIPTS}
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