Searched refs:family (Results 1 – 25 of 78) sorted by relevance
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| /toolchain/binutils/binutils-2.25/cpu/ |
| D | or1k.cpu | 22 ; The OpenRISC family is a set of RISC microprocessor architectures with an
63 (comment "OpenRISC 1000 32-bit CPU family")
106 (comment "OpenRISC 1000 64-bit CPU family")
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| D | sh.cpu | 52 ; CPU family.
56 (comment "SH 64-bit family")
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| D | mt.cpu | 32 (name mt) ; name of cpu family
33 (comment "Morpho Technologies mRISC family")
51 ; Cpu family definitions.
57 (comment "Morpho Technologies mRISC family")
65 (comment "Morpho Technologies mRISC family")
73 (comment "Morpho Technologies mRISC family")
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| D | m32r.cpu | 34 (name m32r) ; name of cpu family
150 ; Cpu family definitions.
152 ; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
164 ; The "f" suffix stands for "family" and is the convention.
166 (comment "Renesas M32R base family")
176 (comment "Renesas M32Rx family")
185 (comment "Renesas M32R2 family")
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| D | lm32.cpu | 25 (name lm32) ; name of cpu family
46 ; Cpu family definitions.
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| /toolchain/binutils/binutils-2.25/gas/doc/ |
| D | c-h8300.texi | 133 The H8/300 family has no hardware floating point, but the @code{.float}
153 for the H8/300 family.
158 for the H8/300 family.
163 the usual (16-bit) for the H8/300 family.
168 the usual (16-bit) for the H8/300 family.
171 On the H8/300 family (including the H8/300H) @samp{.word} directives
186 pseudo-instructions are needed on this family.
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| D | c-m32c.texi | 17 the Renesas M32C family. Normally the default is to assemble code for
117 address into a 16 bit register. While the M32C family only has 24
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| D | c-m68k.texi | 156 Motorola 680x0 family. The default depends upon how @code{@value{AS}}
160 addressing modes are permitted. The members of the 680x0 family are
209 Assemble for the CPU32 family of chips.
225 Assemble for the ColdFire family of chips.
539 Here, @samp{j@var{XX}} stands for an entire family of pseudo-operations,
541 list of pseudo-ops in this family is:
563 The full family of pseudo-operations covered here is
592 This family includes
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| D | c-ppc.texi | 29 The PowerPC chip family includes several successive levels, using the same
112 Generate code for PowerPC e300 family.
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| D | c-microblaze.texi | 15 The Xilinx MicroBlaze processor family includes several variants, all using
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| D | c-sh.texi | 23 (formerly Hitachi) / SuperH SH family.
237 pseudo-instructions are needed on this family. Note, however, that
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| D | c-m68hc11.texi | 63 co-processor featured on some S12X-family chips.
452 Here, @samp{jb@var{XX}} stands for an entire family of pseudo-operations,
454 list of pseudo-ops in this family is:
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| D | c-msp430.texi | 236 The MSP 430 family uses @sc{ieee} 32-bit floating-point numbers.
290 additional pseudo-instructions are needed on this family.
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| D | c-v850.texi | 22 for the V850 processor family:
267 The V850 family uses @sc{ieee} floating-point numbers.
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| D | c-nds32.texi | 17 The NDS32 processors family includes high-performance and low-power 32-bit
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| D | c-z80.texi | 70 The assembler syntax closely follows the 'Z80 family CPU User Manual' by
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| D | c-bfin.texi | 233 The Blackfin family has no hardware floating point but the .float
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| /toolchain/binutils/binutils-2.25/bfd/ |
| D | ieee.c | 1833 char family[10]; in ieee_object_p() local
1848 strcpy (family, "68000"); /* MC68000-based controllers. */ in ieee_object_p()
1855 strcpy (family, "68332"); /* CPU32 and CPU32+ */ in ieee_object_p()
1860 strcpy (family, "68030"); /* CPU030 */ in ieee_object_p()
1862 strcpy (family, "68332"); /* CPU32 and CPU32+ */ in ieee_object_p()
1866 strcpy (family, "68332"); /* Guess it will be CPU32 */ in ieee_object_p()
1870 strcpy (family, "68332"); /* CPU32 */ in ieee_object_p()
1876 strcpy (family, "68"); in ieee_object_p()
1877 strncat (family, processor + 4, 7); in ieee_object_p()
1878 family[9] = '\0'; in ieee_object_p()
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| D | rex.s | 19 # Test prefixes family.
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| D | pfmam.s | 1 # pfmam.p family (p={ss,sd,dd})
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| D | pfam.s | 1 # pfam.p family (p={ss,sd,dd})
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| D | pfmsm.s | 1 # pfmsm.p family (p={ss,sd,dd})
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| D | pfsm.s | 1 # pfsm.p family (p={ss,sd,dd})
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| /toolchain/binutils/binutils-2.25/libiberty/ |
| D | libiberty.texi | 158 or ``family'' of operating systems. As an example, the @code{bzero}
160 family of systems.
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| /toolchain/binutils/binutils-2.25/ld/emultempl/ |
| D | avrelf.em | 23 # routines. It is used to generate the trampolines for the avr6 family
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