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/toolchain/binutils/binutils-2.25/gas/config/
Dtc-pdp11.c651 struct pdp11_code insn, op1, op2; in md_assemble() local
686 op1.error = NULL; in md_assemble()
687 op1.additional = FALSE; in md_assemble()
688 op1.reloc.type = BFD_RELOC_NONE; in md_assemble()
710 str = parse_expression (str, &op1); in md_assemble()
711 if (op1.error) in md_assemble()
713 if (op1.reloc.exp.X_op != O_constant || op1.reloc.type != BFD_RELOC_NONE) in md_assemble()
715 op1.error = _("operand is not an absolute constant"); in md_assemble()
721 if (op1.reloc.exp.X_add_number & ~7) in md_assemble()
723 op1.error = _("3-bit immediate out of range"); in md_assemble()
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Dtc-msp430.c167 int op1; /* Opcode for second word of short jump. */ member
1541 struct msp430_operand_s * op1, in try_encode_mova() argument
1553 if (op1->mode == OP_EXP) in try_encode_mova()
1562 if (op1->am == 3) in try_encode_mova()
1568 if (op1->exp.X_op == O_constant) in try_encode_mova()
1570 bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8; in try_encode_mova()
1572 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2); in try_encode_mova()
1577 fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE, in try_encode_mova()
1584 else if (op1->am == 1) in try_encode_mova()
1587 bin |= 0x30 | (op1->reg << 8) | op2->reg; in try_encode_mova()
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Dxtensa-relax.c582 unsigned op1, in append_value_condition() argument
588 cond->op_num = op1; in append_value_condition()
598 unsigned op1, in append_constant_value_condition() argument
604 cond->op_num = op1; in append_constant_value_condition()
655 append_literal_op (BuildInstr *bi, unsigned op1, unsigned src_op) in append_literal_op() argument
659 b_op->op_num = op1; in append_literal_op()
668 append_label_op (BuildInstr *bi, unsigned op1) in append_label_op() argument
672 b_op->op_num = op1; in append_label_op()
681 append_constant_op (BuildInstr *bi, unsigned op1, unsigned cnst) in append_constant_op() argument
685 b_op->op_num = op1; in append_constant_op()
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Dtc-d10v.c693 check_resource_conflict (struct d10v_opcode *op1, in check_resource_conflict() argument
702 if ((op1->exec_type & SEQ) in check_resource_conflict()
703 || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY))) in check_resource_conflict()
706 op1->name); in check_resource_conflict()
743 op = op1; in check_resource_conflict()
829 parallel_ok (struct d10v_opcode *op1, in parallel_ok() argument
839 if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0 in parallel_ok()
840 || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0 in parallel_ok()
841 || (op1->unit == BOTH) || (op2->unit == BOTH) in parallel_ok()
842 || (op1->unit == IU && op2->unit == IU) in parallel_ok()
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Dtc-d30v.c494 opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18; in build_insn()
679 parallel_ok (struct d30v_insn *op1, in parallel_ok() argument
692 if ((op1->op->unit == IU && op2->op->unit == IU) in parallel_ok()
693 || (op1->op->unit == MU && op2->op->unit == MU)) in parallel_ok()
699 && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))) in parallel_ok()
705 if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX) in parallel_ok()
706 || (op1->ecc == ECC_FX && op2->ecc == ECC_TX) in parallel_ok()
707 || (op1->ecc == ECC_XT && op2->ecc == ECC_XF) in parallel_ok()
708 || (op1->ecc == ECC_XF && op2->ecc == ECC_XT)) in parallel_ok()
718 f = op1->form; in parallel_ok()
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Dtc-bfin.c1180 bfin_gen_dsp32mac (int op1, int MM, int mmod, int w1, int P, in bfin_gen_dsp32mac() argument
1187 ASSIGN (op1); in bfin_gen_dsp32mac()
1213 bfin_gen_dsp32mult (int op1, int MM, int mmod, int w1, int P, in bfin_gen_dsp32mult() argument
1220 ASSIGN (op1); in bfin_gen_dsp32mult()
2271 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); in decode_dsp32mac_0() local
2280 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) in decode_dsp32mac_0()
2283 if (op1 == 3 && MM) in decode_dsp32mac_0()
2292 if (w1 == 1 || op1 != 3) in decode_dsp32mac_0()
Dbfin-parse.y32 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \ argument
33 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
36 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \ argument
37 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
739 int op0, op1; variable
750 op1 = 3;
760 op1 = $1.op;
768 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
Dtc-cr16.c1520 char op1[5]; in get_b_cc() local
1523 op1[i-1] = op[i]; in get_b_cc()
1525 op1[i-1] = '\0'; in get_b_cc()
1528 if (streq (op1, cr16_b_cond_tab[i])) in get_b_cc()
/toolchain/binutils/binutils-2.25/opcodes/
Dmsp430-dis.c85 print_as2_reg_name (int regno, char * op1, char * comm1, in print_as2_reg_name() argument
91 sprintf (op1, "#4"); in print_as2_reg_name()
96 sprintf (op1, "#2"); in print_as2_reg_name()
102 sprintf (op1, "@r%d", regno); in print_as2_reg_name()
108 print_as3_reg_name (int regno, char * op1, char * comm1, in print_as3_reg_name() argument
114 sprintf (op1, "#8"); in print_as3_reg_name()
119 sprintf (op1, "#-1"); in print_as3_reg_name()
125 sprintf (op1, "@r%d+", regno); in print_as3_reg_name()
367 char *op1, in msp430_doubleoperand() argument
416 sprintf (op1, "r%d", regd); in msp430_doubleoperand()
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Dsparc-dis.c254 sparc_opcode *op1 = * (sparc_opcode **) b; in compare_opcodes() local
255 unsigned long int match0 = op0->match, match1 = op1->match; in compare_opcodes()
256 unsigned long int lose0 = op0->lose, lose1 = op1->lose; in compare_opcodes()
266 if (! (op1->architecture & current_arch_mask)) in compare_opcodes()
271 if (op1->architecture & current_arch_mask) in compare_opcodes()
273 else if (op0->architecture != op1->architecture) in compare_opcodes()
274 return op0->architecture - op1->architecture; in compare_opcodes()
296 op1->name, match1, lose1); in compare_opcodes()
297 op1->lose &= ~op1->match; in compare_opcodes()
298 lose1 = op1->lose; in compare_opcodes()
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Davr-dis.c296 char op1[20], op2[20], comment1[40], comment2[40]; in print_insn_avr() local
356 op1[0] = 0; in print_insn_avr()
379 …ok = avr_operand (insn, insn2, addr, *constraints, opcode_str, op1, comment1, 0, &sym_op1, &sym_ad… in print_insn_avr()
390 sprintf (op1, "0x%04x", insn); in print_insn_avr()
398 if (*op1) in print_insn_avr()
399 (*prin) (stream, "\t%s", op1); in print_insn_avr()
Dd30v-dis.c39 int op1 = (num >> 25) & 0x7; in lookup_opcode() local
46 if ((op->op1 == op1) && (op->op2 == op2)) in lookup_opcode()
55 while (op->op1 == op1 && op->op2 == op2) in lookup_opcode()
Daarch64-opc.c2697 #define CPENC(op0,op1,crn,crm,op2) \ argument
2698 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
2700 #define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2)) argument
2702 #define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2)) argument
Darc-dis.c196 int op1, in instruction_name() argument
201 return (*state->instName)(state->_this, op1, op2, flags); in instruction_name()
Drl78-decode.opc172 int op0, op1;
750 op1 = IMMU(1);
751 ID(mov); DM(None, op0); SC(op1);
753 switch (op1)
/toolchain/binutils/binutils-2.25/cpu/
Dxc16x.cpu141 (dnf f-op1 "op1" () 7 4)
194 ; insn-op1: bits 0-3
195 (define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
665 (define-pmacro (arithmetic16 name insn insn1 opc1 opc2 op1 op2 mode dir)
669 (.str insn " $"op1 ",$"dir"$"op2)
670 (+ opc1 opc2 op1 op2)
671 (set mode op1 (insn1 mode op1 (mem HI op2)))
685 (define-pmacro (arithmetic17 name insn insn1 opc1 opc2 op1 op2 mode dir)
689 (.str insn " $"op1 ",$"dir"$"op2)
690 (+ opc1 opc2 op1 op2)
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Dmt.cpu663 (sequence((HI op1) (HI op2))
664 (set op1 (and frsr1 #xffff))
665 (if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
672 (set frdrrr (mul SI (ext SI op1) (ext SI op2)))
681 (sequence((HI op1) (HI op2))
682 (set op1 (and frsr1 #xffff))
683 (if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
687 (if (eq op1 (const 0))
688 (error "op1 is 0")
693 (set frdr (mul SI (ext SI op1) (ext SI op2)))
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/
Dsysreg-1.s133 .macro all_op2 op1, crn, crm, from=0, to=7
134 rw_sys_reg S3_\op1\()_C\crn\()_C\crm\()_\from x15 1 1
136 all_op2 \op1, \crn, \crm, %(\from+1), \to
140 .macro all_crm op1, crn, from=0, to=15
141 all_op2 \op1, \crn, \from, 0, 7
143 all_crm \op1, \crn, %(\from+1), \to
/toolchain/binutils/binutils-2.25/bfd/
Dvms-alpha.c1694 bfd_vma op1; in _bfd_vms_slurp_etir() local
1729 _bfd_vms_get_value (abfd, ptr, info, &op1, &h); in _bfd_vms_slurp_etir()
1730 _bfd_vms_push (abfd, op1, alpha_vms_sym_to_ctxt (h)); in _bfd_vms_slurp_etir()
1767 op1 = bfd_getl64 (ptr + 4); in _bfd_vms_slurp_etir()
1768 _bfd_vms_push (abfd, op1, psect | RELC_SEC_BASE); in _bfd_vms_slurp_etir()
1783 _bfd_vms_pop (abfd, &op1, &rel1); in _bfd_vms_slurp_etir()
1786 image_write_b (abfd, (unsigned int) op1 & 0xff); in _bfd_vms_slurp_etir()
1792 _bfd_vms_pop (abfd, &op1, &rel1); in _bfd_vms_slurp_etir()
1795 image_write_w (abfd, (unsigned int) op1 & 0xffff); in _bfd_vms_slurp_etir()
1801 _bfd_vms_pop (abfd, &op1, &rel1); in _bfd_vms_slurp_etir()
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Delf32-h8300.c1233 unsigned char op0, op1, op2, op3; in elf32_h8_relax_section() local
1285 op1 = bfd_get_8 (abfd, op_ptr + 1); in elf32_h8_relax_section()
1290 && (op1 & 0xdf) == 0x5f in elf32_h8_relax_section()
1314 op1 = bfd_get_8 (abfd, op_ptr + 1); in elf32_h8_relax_section()
1317 && (op1 & 0x88) == 0x80) in elf32_h8_relax_section()
1319 op1 |= 0x08; in elf32_h8_relax_section()
1320 bfd_put_8 (abfd, op1, op_ptr + 1); in elf32_h8_relax_section()
1377 unsigned char op0, op1, op2, op3, op0n, op1n; in elf32_h8_relax_section() local
1389 op1 = bfd_get_8 (abfd, contents + irel->r_offset - 3); in elf32_h8_relax_section()
1398 if ((op1 & 0x8F) == 0x00 && (op3 & 0x70) == 0x20) in elf32_h8_relax_section()
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Dcoff-sh.c2195 const struct sh_opcode *op1, in sh_insns_conflict() argument
2201 f1 = op1->flags; in sh_insns_conflict()
2236 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2))) in sh_insns_conflict()
2239 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2))) in sh_insns_conflict()
2242 && sh_insn_uses_or_sets_reg (i1, op1, 0)) in sh_insns_conflict()
2245 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2))) in sh_insns_conflict()
2248 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2))) in sh_insns_conflict()
2260 const struct sh_opcode *op1, in sh_load_use() argument
2266 f1 = op1->flags; in sh_load_use()
/toolchain/binutils/binutils-2.25/gold/
Di386.cc3259 unsigned char op1 = view[-1]; in tls_gd_to_le() local
3273 ((op1 & 0xc7) == 0x05 && op1 != (4 << 3))); in tls_gd_to_le()
3279 (op1 & 0xf8) == 0x80 && (op1 & 7) != 4); in tls_gd_to_le()
3321 unsigned char op1 = view[-1]; in tls_gd_to_ie() local
3338 ((op1 & 0xc7) == 0x05 && op1 != (4 << 3))); in tls_gd_to_ie()
3344 (op1 & 0xf8) == 0x80 && (op1 & 7) != 4); in tls_gd_to_ie()
3501 unsigned char op1 = view[-1]; in tls_ie_to_le() local
3502 if (op1 == 0xa1) in tls_ie_to_le()
3516 (op1 & 0xc7) == 0x05); in tls_ie_to_le()
3518 view[-1] = 0xc0 | ((op1 >> 3) & 7); in tls_ie_to_le()
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/toolchain/binutils/binutils-2.25/include/opcode/
Dd30v.h77 int op1; /* first part, "IALU1" for example */ member
Dm88k.h441 OPSPEC op1,op2,op3; member
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dneon-cov.s592 .macro binop_3typ op op1 op2 t1 t2 t3
593 \op\t1 \op1,\op2
594 \op\t2 \op1,\op2
595 \op\t3 \op1,\op2

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