Searched refs:AMDGPUInstrInfo (Results 1 – 24 of 24) sorted by relevance
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.cpp | 29 AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) in AMDGPUInstrInfo() function in AMDGPUInstrInfo
32 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { in getRegisterInfo()
36 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
43 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, in isLoadFromStackSlot()
49 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, in isLoadFromStackSlotPostFE()
55 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, in hasLoadFromStackSlot()
61 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, in isStoreFromStackSlot()
66 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, in isStoreFromStackSlotPostFE()
71 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, in hasStoreFromStackSlot()
79 AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, in convertToThreeAddress()
[all …]
|
| D | AMDGPU.td | 14 def AMDGPUInstrInfo : InstrInfo {}
27 let InstructionSet = AMDGPUInstrInfo;
35 include "AMDGPUInstrInfo.td"
|
| D | AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII = in runOnMachineFunction()
50 static_cast<const AMDGPUInstrInfo*>(TM.getInstrInfo()); in runOnMachineFunction()
|
| D | AMDGPUTargetMachine.h | 35 const AMDGPUInstrInfo * InstrInfo;
53 virtual const AMDGPUInstrInfo *getInstrInfo() const {return InstrInfo;} in getInstrInfo()
|
| D | Makefile.sources | 4 AMDGPUInstrInfo.td \
63 AMDGPUInstrInfo.cpp \
|
| D | AMDGPUInstrInfo.h | 40 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
47 explicit AMDGPUInstrInfo(TargetMachine &tm);
|
| D | SIInstrInfo.h | 23 class SIInstrInfo : public AMDGPUInstrInfo {
|
| D | SIInstrInfo.cpp | 26 : AMDGPUInstrInfo(tm), in SIInstrInfo()
|
| D | R600InstrInfo.h | 32 class R600InstrInfo : public AMDGPUInstrInfo {
|
| D | AMDGPUInstrInfo.td | 1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
|
| D | R600InstrInfo.cpp | 28 : AMDGPUInstrInfo(tm), in R600InstrInfo()
362 return AMDGPUInstrInfo::isPredicable(MI); in isPredicable()
|
| D | AMDILCFGStructurizer.cpp | 1903 const AMDGPUInstrInfo *tii = in addLoopEndbranchBlock()
1904 static_cast<const AMDGPUInstrInfo *>(passRep->getTargetInstrInfo()); in addLoopEndbranchBlock()
2928 const AMDGPUInstrInfo * TII = static_cast<const AMDGPUInstrInfo *>( in getLoopendBlockBranchInstr()
3119 const AMDGPUInstrInfo *tii = in insertAssignInstrBefore()
3120 static_cast<const AMDGPUInstrInfo *>(passRep->getTargetInstrInfo()); in insertAssignInstrBefore()
3132 const AMDGPUInstrInfo *tii = in insertAssignInstrBefore()
3133 static_cast<const AMDGPUInstrInfo *>(passRep->getTargetInstrInfo()); in insertAssignInstrBefore()
3152 const AMDGPUInstrInfo *tii = in insertCompareInstrBefore()
3153 static_cast<const AMDGPUInstrInfo *>(passRep->getTargetInstrInfo()); in insertCompareInstrBefore()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstrInfo.cpp | 31 void AMDGPUInstrInfo::anchor() {} in anchor()
33 AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &st) in AMDGPUInstrInfo() function in AMDGPUInstrInfo
36 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { in getRegisterInfo()
40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, in isLoadFromStackSlot()
53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, in isLoadFromStackSlotPostFE()
59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, in hasLoadFromStackSlot()
65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, in isStoreFromStackSlot()
70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, in isStoreFromStackSlotPostFE()
75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, in hasStoreFromStackSlot()
[all …]
|
| D | AMDGPUSubtarget.h | 94 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
107 const AMDGPUInstrInfo *getInstrInfo() const override { in getInstrInfo()
|
| D | AMDGPUInstrInfo.h | 40 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
47 explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
|
| D | AMDGPU.td | 244 def AMDGPUInstrInfo : InstrInfo {
257 let InstructionSet = AMDGPUInstrInfo;
290 include "AMDGPUInstrInfo.td"
|
| D | CMakeLists.txt | 33 AMDGPUInstrInfo.cpp
|
| D | R600InstrInfo.h | 32 class R600InstrInfo : public AMDGPUInstrInfo {
|
| D | AMDGPUInstrInfo.td | 1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
|
| D | R600InstrInfo.cpp | 32 : AMDGPUInstrInfo(st), RI() {} in R600InstrInfo()
916 return AMDGPUInstrInfo::isPredicable(MI); in isPredicable()
1053 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI); in expandPostRAPseudo()
|
| D | SIInstrInfo.h | 25 class SIInstrInfo : public AMDGPUInstrInfo {
|
| D | SILowerControlFlow.cpp | 580 = static_cast<const AMDGPUInstrInfo*>(TII)->getIndirectIndexBegin(MF); in runOnMachineFunction()
|
| D | SIInstrInfo.cpp | 31 : AMDGPUInstrInfo(st), RI() {} in SIInstrInfo()
794 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI); in expandPostRAPseudo()
|
| D | SIInstrInfo.td | 85 // in AMDGPUInstrInfo.cpp
|