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Searched refs:ImmOp (Results 1 – 21 of 21) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
DR600MCCodeEmitter.cpp250 MCOperand ImmOp = MI.getOperand(ImmOpIndex); in EmitSrc() local
251 if (ImmOp.isFPImm()) { in EmitSrc()
252 Value.f = ImmOp.getFPImm(); in EmitSrc()
254 assert(ImmOp.isImm()); in EmitSrc()
255 Value.i = ImmOp.getImm(); in EmitSrc()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td1260 Operand ImmOp, bits<2>MajOp>
1262 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1342 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1345 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1411 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1413 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1422 string ImmOpStr = !cast<string>(ImmOp);
1444 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1448 ImmOp:$offset, IntRegs:$src3),
1459 string ImmOpStr = !cast<string>(ImmOp);
[all …]
DHexagonInstrInfoV60.td106 class T_vstore_ai <string mnemonic, string baseOp, Operand ImmOp,
108 : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
146 class T_vstore_new_ai <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
147 : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
175 class T_vstore_pred_ai <string mnemonic, string baseOp, Operand ImmOp,
178 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
237 class T_vstore_qpred_ai <Operand ImmOp, RegisterClass RC,
240 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
276 class T_vstore_new_pred_ai <string baseOp, Operand ImmOp, RegisterClass RC,
279 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
[all …]
DHexagonInstrInfo.td68 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
70 (ins IntRegs:$src1, ImmOp:$src2),
1620 Operand ImmOp>
1621 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1629 string ImmOpStr = !cast<string>(ImmOp);
1652 Operand ImmOp, bit isNot, bit isPredNew>
1654 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1664 string ImmOpStr = !cast<string>(ImmOp);
1694 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1697 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
[all …]
/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp387 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteFrameIndex() local
394 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteFrameIndex()
411 ImmOp.ChangeToImmediate(0); in rewriteFrameIndex()
415 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteFrameIndex()
DThumb2InstrInfo.cpp588 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1); in rewriteT2FrameIndex() local
604 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteT2FrameIndex()
622 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteT2FrameIndex()
DARMBaseInstrInfo.cpp2243 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteARMFrameIndex() local
2258 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteARMFrameIndex()
2271 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteARMFrameIndex()
/external/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp290 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue()); in foldOperand() local
291 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII); in foldOperand()
/external/llvm/lib/Target/X86/AsmParser/
DX86Operand.h48 struct ImmOp { struct
65 struct ImmOp Imm;
DX86AsmParser.cpp2125 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, in ParseInstruction() local
2127 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); in ParseInstruction()
2152 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, in ParseInstruction() local
2154 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); in ParseInstruction()
2179 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, in ParseInstruction() local
2181 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); in ParseInstruction()
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp300 unsigned ImmOp = Inst.getNumOperands() - 1; in SimplifyShortImmForm() local
302 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && in SimplifyShortImmForm()
313 MCOperand Saved = Inst.getOperand(ImmOp); in SimplifyShortImmForm()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp188 struct ImmOp { struct in __anoncba7d3b40111::SparcOperand
201 struct ImmOp Imm;
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp617 struct ImmOp { struct in __anond0efcad40311::MipsOperand
634 struct ImmOp Imm;
2320 const MCOperand &ImmOp = Inst.getOperand(1); in expandLoadImm() local
2321 assert(ImmOp.isImm() && "expected immediate operand kind"); in expandLoadImm()
2325 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, in expandLoadImm()
2512 const MCOperand &ImmOp = Inst.getOperand(1); in expandBranchImm() local
2513 assert(ImmOp.isImm() && "expected immediate operand kind"); in expandBranchImm()
2531 int64_t ImmValue = ImmOp.getImm(); in expandBranchImm()
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp78 struct ImmOp { struct in __anon2fa8e53e0111::AMDGPUOperand
94 ImmOp Imm;
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td348 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :
349 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
DMipsMSAInstrInfo.td1177 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1181 dag InOperandList = (ins ROWS:$ws, ImmOp:$m);
1240 Operand ImmOp, ImmLeaf Imm,
1243 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n);
1468 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1472 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2);
DMipsDSPInstrInfo.td381 Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
383 dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
DMipsSEISelLowering.cpp1413 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { in lowerMSASplatImm() argument
1414 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), SDLoc(Op), in lowerMSASplatImm()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp191 struct ImmOp { struct in __anon26fd99540211::AArch64Operand
253 struct ImmOp Imm;
4036 AArch64Operand &ImmOp = static_cast<AArch64Operand &>(*Operands[2]); in MatchAndEmitInstruction() local
4037 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) { in MatchAndEmitInstruction()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp484 struct ImmOp { struct in __anonef5d38c20311::ARMOperand
555 struct ImmOp Imm;
4636 int CondOp = -1, ImmOp = -1; in cvtThumbBranches() local
4639 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; in cvtThumbBranches()
4642 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; in cvtThumbBranches()
4675 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
4682 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
4688 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); in cvtThumbBranches()
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp337 struct ImmOp { struct
352 struct ImmOp Imm;