| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 266 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
276 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
281 unsigned getIndexReg() { return IndexReg; } in getIndexReg()
389 assert (!IndexReg && "BaseReg/IndexReg already set!"); in onPlus()
390 IndexReg = TmpReg; in onPlus()
426 assert (!IndexReg && "BaseReg/IndexReg already set!"); in onMinus()
427 IndexReg = TmpReg; in onMinus()
463 assert (!IndexReg && "IndexReg already set!"); in onRegister()
465 IndexReg = Reg; in onRegister()
513 assert (!IndexReg && "IndexReg already set!"); in onInteger()
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| D | X86Operand.h | 56 unsigned IndexReg; member
121 return Mem.IndexReg; in getMemIndexReg()
503 Res->Mem.IndexReg = 0;
516 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
521 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
530 Res->Mem.IndexReg = IndexReg;
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 49 unsigned IndexReg; member
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
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| D | X86AsmPrinter.cpp | 246 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printLeaMemReference() local
256 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
276 assert(IndexReg.getReg() != X86::ESP && in printLeaMemReference()
283 if (IndexReg.getReg()) { in printLeaMemReference()
312 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printIntelMemReference() local
330 if (IndexReg.getReg()) { in printIntelMemReference()
343 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printIntelMemReference()
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| D | X86ISelDAGToDAG.cpp | 62 SDValue IndexReg; member
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
114 if (IndexReg.getNode()) in dump()
115 IndexReg.getNode()->dump(); in dump()
255 Index = AM.IndexReg; in getAddressOperands()
846 AM.Base_Reg = AM.IndexReg; in matchAddress()
858 AM.IndexReg.getNode() == nullptr && in matchAddress()
889 !AM.IndexReg.getNode()) { in matchAdd()
892 AM.IndexReg = N.getOperand(1); in matchAdd()
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| D | X86FastISel.cpp | 257 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
596 (AM.Base.Reg == 0 && AM.IndexReg == 0)) { in handleConstantAddresses()
615 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in handleConstantAddresses()
677 if (AM.IndexReg == 0) { in handleConstantAddresses()
679 AM.IndexReg = getRegForValue(V); in handleConstantAddresses()
680 return AM.IndexReg != 0; in handleConstantAddresses()
764 unsigned IndexReg = AM.IndexReg; in X86SelectAddress() local
796 if (IndexReg == 0 && in X86SelectAddress()
801 IndexReg = getRegForGEPIndex(Op).first; in X86SelectAddress()
802 if (IndexReg == 0) in X86SelectAddress()
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| D | X86MCInstLower.cpp | 797 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in EmitNops() local
798 Opc = IndexReg = Displacement = SegmentReg = 0; in EmitNops()
807 IndexReg = X86::RAX; break; in EmitNops()
809 IndexReg = X86::RAX; break; in EmitNops()
812 IndexReg = X86::RAX; break; in EmitNops()
814 IndexReg = X86::RAX; break; in EmitNops()
816 IndexReg = X86::RAX; SegmentReg = X86::CS; break; in EmitNops()
835 .addImm(ScaleVal).addReg(IndexReg) in EmitNops()
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| D | X86ISelLowering.cpp | 22405 AM.IndexReg = Op.getImm(); in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is16BitMemOperand() local
69 (IndexReg.getReg() != 0 && in Is16BitMemOperand()
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) in Is16BitMemOperand()
227 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand() local
231 (IndexReg.getReg() != 0 && in Is32BitMemOperand()
232 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in Is32BitMemOperand()
242 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is64BitMemOperand() local
246 (IndexReg.getReg() != 0 && in Is64BitMemOperand()
247 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) in Is64BitMemOperand()
371 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in EmitMemModRMByte() local
[all …]
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 190 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
204 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
211 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
216 if (IndexReg.getReg()) { in printMemReference()
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| D | X86IntelInstPrinter.cpp | 161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
179 if (IndexReg.getReg()) { in printMemReference()
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 162 unsigned &IndexReg);
419 unsigned &IndexReg) { in PPCSimplifyAddress() argument
441 IndexReg = PPCMaterializeInt(Offset, MVT::i64); in PPCSimplifyAddress()
442 assert(IndexReg && "Unexpected error in PPCMaterializeInt!"); in PPCSimplifyAddress()
506 unsigned IndexReg = 0; in PPCEmitLoad() local
507 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg); in PPCEmitLoad()
570 .addReg(Addr.Base.Reg).addReg(IndexReg); in PPCEmitLoad()
642 unsigned IndexReg = 0; in PPCEmitStore() local
643 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg); in PPCEmitStore()
709 if (IndexReg) in PPCEmitStore()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 442 unsigned SavReg, unsigned IndexReg) const;
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 4927 unsigned IndexReg = MI->getOperand(3).getReg(); in emitCondStore() local
4937 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) { in emitCondStore()
4969 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg); in emitCondStore()
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| /external/llvm/docs/ |
| D | CodeGenerator.rst | 2174 SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
2183 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
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