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Searched refs:PrintReg (Results 1 – 25 of 46) sorted by relevance

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/external/llvm/lib/CodeGen/
DLiveRegMatrix.cpp98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
99 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign()
116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
117 << " from " << PrintReg(PhysReg, TRI) << ':'); in unassign()
DRegAllocFast.cpp285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI) in spillVirtReg()
286 << " in " << PrintReg(LR.PhysReg, TRI)); in spillVirtReg()
450 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n"); in calcSpillCost()
459 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding " in calcSpillCost()
460 << PrintReg(PhysReg, TRI) << " is reserved already.\n"); in calcSpillCost()
470 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n"); in calcSpillCost()
499 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to " in assignVirtToPhysReg()
500 << PrintReg(PhysReg, TRI) << "\n"); in assignVirtToPhysReg()
554 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from " in allocVirtReg()
560 DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n"); in allocVirtReg()
[all …]
DRegAllocGreedy.cpp633 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n'); in tryAssign()
649 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost in tryAssign()
680 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI) in canReassign()
814 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI) in evictInterference()
898 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " in tryEvict()
899 << PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in tryEvict()
1412 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n"); in calculateRegionSplitCost()
1415 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = "; in calculateRegionSplitCost()
1423 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; in calculateRegionSplitCost()
1472 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in " in doRegionSplit()
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DRegisterCoalescer.cpp529 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI)); in adjustCopiesBackFrom()
1342 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI) in joinCopy()
1343 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) in joinCopy()
1365 dbgs() << PrintReg(CP.getDstReg()) << " in " in joinCopy()
1367 << PrintReg(CP.getSrcReg()) << " in " in joinCopy()
1370 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in " in joinCopy()
1371 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; in joinCopy()
1457 dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) in joinCopy()
1458 << " -> " << PrintReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; in joinCopy()
1461 dbgs() << PrintReg(CP.getDstReg(), TRI); in joinCopy()
[all …]
DInlineSpiller.cpp321 OS << "spill " << PrintReg(SVI.SpillReg) << ':' in operator <<()
498 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':' in traceSiblingValue()
503 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':' in traceSiblingValue()
516 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def in traceSiblingValue()
605 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':' in traceSiblingValue()
678 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@' in analyzeSiblingValues()
703 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n'); in hoistSpill()
710 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n'); in hoistSpill()
1217 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n'); in spillAroundUses()
1384 << "\nFrom original " << PrintReg(Original) << '\n'); in spill()
DMachineRegisterInfo.cpp129 errs() << PrintReg(Reg, getTargetRegisterInfo()) in verifyUseList()
138 errs() << PrintReg(Reg, getTargetRegisterInfo()) in verifyUseList()
144 errs() << PrintReg(Reg, getTargetRegisterInfo()) in verifyUseList()
150 errs() << PrintReg(Reg, getTargetRegisterInfo()) in verifyUseList()
DAllocationOrder.cpp45 dbgs() << ' ' << PrintReg(Hints[I], TRI); in AllocationOrder()
DVirtRegMap.cpp125 OS << '[' << PrintReg(Reg, TRI) << " -> " in print()
126 << PrintReg(Virt2PhysMap[Reg], TRI) << "] " in print()
134 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] in print()
DTargetRegisterInfo.cpp45 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, in PrintReg() function
395 dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
DRegAllocPBQP.cpp639 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: " in spillVReg()
648 DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " "); in spillVReg()
678 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> " in mapPBQPToRegAlloc()
817 OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')'; in PrintNodeInfo()
DLivePhysRegs.cpp118 OS << " " << PrintReg(*I, TRI); in print()
DLiveRangeCalc.cpp276 errs() << "Use of " << PrintReg(PhysReg) in findReachingDefs()
287 errs() << "The register " << PrintReg(PhysReg) in findReachingDefs()
DRegisterClassInfo.cpp145 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); in compute()
DLiveIntervalUnion.cpp89 << PrintReg(SI.value()->reg, TRI); in print()
DPHIElimination.cpp261 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi); in LowerPHINode()
585 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#" in SplitPHIEdges()
DScheduleDAG.cpp351 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI); in dumpAll()
371 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI); in dumpAll()
/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRLiveRanges.cpp182 DEBUG(dbgs() << PrintReg(Reg, TRI, 0) in runOnMachineFunction()
188 DEBUG(dbgs() << PrintReg(Reg, TRI, 0) in runOnMachineFunction()
196 << PrintReg(Reg, TRI, 0) in runOnMachineFunction()
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp250 DEBUG(dbgs() << "Moving acc chain from " << PrintReg(Ra, TRI) << " to " in addInterChainConstraint()
251 << PrintReg(Rd, TRI) << '\n';); in addInterChainConstraint()
256 DEBUG(dbgs() << "Creating new acc chain for " << PrintReg(Rd, TRI) in addInterChainConstraint()
343 DEBUG(dbgs() << "Killing chain " << PrintReg(r, TRI) << " at "; in apply()
DAArch64FrameLowering.cpp945 DEBUG(dbgs() << ' ' << PrintReg(OddReg, RegInfo)); in determineCalleeSaves()
946 DEBUG(dbgs() << ' ' << PrintReg(EvenReg, RegInfo)); in determineCalleeSaves()
995 DEBUG(dbgs() << "Spilling " << PrintReg(Reg, RegInfo) in determineCalleeSaves()
/external/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp173 OS << ' ' << PrintReg(R, P.TRI); in operator <<()
404 OS << PrintReg(*I, P.TRI); in operator <<()
450 OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI) in operator <<()
544 dbgs() << " " << PrintReg(I->first, HRI) << ":\n"; in dump_map()
762 dbgs() << LLVM_FUNCTION_NAME << ": " << PrintReg(VR, HRI) in findRecordInsertForms()
826 dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n"; in findRecordInsertForms()
831 dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@" in findRecordInsertForms()
879 dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI) in findRecordInsertForms()
880 << ',' << PrintReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms()
1515 dbgs() << PrintReg(VR, HRI) << " -> " << Pos << "\n"; in runOnMachineFunction()
DHexagonGenPredicate.cpp60 return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
208 << PrintReg(Reg.R, TRI, Reg.S) << "\n"); in processPredicateGPR()
212 DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n'); in processPredicateGPR()
DHexagonSplitDouble.cpp128 dbgs() << ' ' << PrintReg(I, &TRI); in dump_partition()
239 DEBUG(dbgs() << PrintReg(R, TRI) << " ~~"); in partitionRegisters()
262 DEBUG(dbgs() << ' ' << PrintReg(T, TRI)); in partitionRegisters()
1125 DEBUG(dbgs() << "Created mapping: " << PrintReg(DR, TRI) << " -> " in splitPartition()
1126 << PrintReg(HiR, TRI) << ':' << PrintReg(LoR, TRI) << '\n'); in splitPartition()
DBitTracker.cpp813 dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) in visitPHI()
820 dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub) in visitPHI()
846 dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) in visitNonBranch()
853 dbgs() << " " << PrintReg(I->first, &ME.TRI) << " cell: " in visitNonBranch()
977 dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n"; in visitUsesOf()
1124 dbgs() << PrintReg(I->first, &ME.TRI) << " -> " << I->second << "\n"; in run()
DHexagonFrameLowering.cpp1188 dbgs() << ' ' << PrintReg(R, &TRI); in dump_registers()
1211 DEBUG(dbgs() << ' ' << PrintReg(R, TRI)); in assignCalleeSavedSpillSlots()
1306 dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp"; in assignCalleeSavedSpillSlots()
1319 dbgs() << PrintReg(R, TRI) << ' '; in assignCalleeSavedSpillSlots()
DHexagonExpandCondsets.cpp443 DEBUG(dbgs() << "adding def " << PrintReg(DefR, TRI) in addInstrToLiveness()
559 DEBUG(dbgs() << "removing def at " << MX << " of " << PrintReg(DefR, TRI) in removeInstrFromLiveness()
1207 << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " in coalesceRegisters()
1208 << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); in coalesceRegisters()

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