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Searched refs:ProcModel (Results 1 – 3 of 3) sorted by relevance

/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp86 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
89 const CodeGenProcModel &ProcModel);
91 const CodeGenProcModel &ProcModel);
93 const CodeGenProcModel &ProcModel);
94 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
424 const CodeGenProcModel &ProcModel = *PI; in EmitStageAndOperandCycleData() local
432 if (!ProcModel.hasItineraries()) in EmitStageAndOperandCycleData()
435 const std::string &Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
438 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins"); in EmitStageAndOperandCycleData()
444 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData()
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DCodeGenSchedule.cpp416 const CodeGenProcModel &ProcModel) const { in expandRWSeqForProc()
425 if (&getProcModel(ModelDef) != &ProcModel) in expandRWSeqForProc()
430 "defined for processor " + ProcModel.ModelName + in expandRWSeqForProc()
436 RWSeq, IsRead,ProcModel); in expandRWSeqForProc()
448 expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel); in expandRWSeqForProc()
556 const CodeGenProcModel &ProcModel = in collectSchedClasses() local
558 ProcIndices.push_back(ProcModel.Index); in collectSchedClasses()
559 dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName; in collectSchedClasses()
771 for (CodeGenProcModel &ProcModel : ProcModels) { in collectProcItins()
772 if (!ProcModel.hasItineraries()) in collectProcItins()
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DCodeGenSchedule.h363 const CodeGenProcModel &ProcModel) const;