Searched refs:ShiftReg (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 1254 unsigned ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr() local
1274 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1281 .addReg(ShiftReg); in EmitShiftInstr()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 517 unsigned ShiftReg; member
1730 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2543 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
2548 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
2838 << " " << RegShiftedReg.ShiftReg << ">"; in print()
3004 int ShiftReg = 0; in tryParseShiftRegister() local
3009 ShiftReg = SrcReg; in tryParseShiftRegister()
3044 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
3045 if (ShiftReg == -1) { in tryParseShiftRegister()
3056 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 8246 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
8291 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
8300 .addReg(incr).addReg(ShiftReg); in EmitPartwordAtomicBinary()
8308 .addReg(Mask2Reg).addReg(ShiftReg); in EmitPartwordAtomicBinary()
8333 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
8963 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
9018 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
9027 .addReg(newval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
9029 .addReg(oldval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
9038 .addReg(Mask2Reg).addReg(ShiftReg); in EmitInstrWithCustomInserter()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3565 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg, in fastLowerIntrinsicCall() local
3569 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true, in fastLowerIntrinsicCall()
3571 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false, in fastLowerIntrinsicCall()
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