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Searched refs:TII (Results 1 – 25 of 256) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyLowerBrUnless.cpp60 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); in runOnMachineFunction() local
78 case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break; in runOnMachineFunction()
79 case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break; in runOnMachineFunction()
80 case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break; in runOnMachineFunction()
81 case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break; in runOnMachineFunction()
82 case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break; in runOnMachineFunction()
83 case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break; in runOnMachineFunction()
84 case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break; in runOnMachineFunction()
85 case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break; in runOnMachineFunction()
86 case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted = true; break; in runOnMachineFunction()
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DWebAssemblyFrameLowering.cpp70 const TargetInstrInfo* TII, in adjustStackPointer() argument
76 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), SPReg) in adjustStackPointer()
84 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::LOAD_I32), SPReg) in adjustStackPointer()
90 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in adjustStackPointer()
93 TII->get(AdjustUp ? WebAssembly::ADD_I32 : WebAssembly::SUB_I32), in adjustStackPointer()
98 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in adjustStackPointer()
102 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32), WebAssembly::SP32) in adjustStackPointer()
112 const auto *TII = in eliminateCallFramePseudoInstr() local
116 bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode(); in eliminateCallFramePseudoInstr()
120 TII, I, DL); in eliminateCallFramePseudoInstr()
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/external/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp35 const R600InstrInfo *TII; member in __anonbccc35610111::R600ExpandSpecialInstrsPass
42 TII(nullptr) { } in R600ExpandSpecialInstrsPass()
61 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
64 TII->setImmOperand(NewMI, Op, Val); in SetFlagInNewMI()
69 TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
71 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
82 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in runOnMachineFunction()
86 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, in runOnMachineFunction()
89 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), in runOnMachineFunction()
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DSIShrinkInstructions.cpp86 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, in canShrink() argument
90 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink()
103 TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers)) in canShrink()
112 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink()
114 TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in canShrink()
121 if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers)) in canShrink()
125 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in canShrink()
128 if (TII->hasModifiersSet(MI, AMDGPU::OpName::clamp)) in canShrink()
138 static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, in foldImmediates() argument
144 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); in foldImmediates()
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DR600Packetizer.cpp61 const R600InstrInfo *TII; member in __anon18a263af0111::R600PacketizerList
76 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
88 if (TII->isPredicated(&*BI)) in getPreviousVector()
90 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); in getPreviousVector()
93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector()
98 if (isTrans || TII->isTransOnly(&*BI)) { in getPreviousVector()
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); in substitutePV()
153 TII(static_cast<const R600InstrInfo *>( in R600PacketizerList()
155 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
173 if (TII->isVector(*MI)) in isSoloInstruction()
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DSILowerControlFlow.cpp73 const SIInstrInfo *TII; member in __anon65737cf30111::SILowerControlFlowPass
98 MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { } in SILowerControlFlowPass()
146 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) in Skip()
164 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in SkipIfDead()
168 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) in SkipIfDead()
180 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); in SkipIfDead()
189 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) in If()
192 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) in If()
208 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) in Else()
211 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) in Else()
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DR600EmitClauseMarkers.cpp38 const R600InstrInfo *TII; member in __anonef5a19be0111::R600EmitClauseMarkers
56 if (TII->isLDSRetInstr(MI->getOpcode())) in OccupiedDwords()
59 if(TII->isVector(*MI) || in OccupiedDwords()
60 TII->isCubeOp(MI->getOpcode()) || in OccupiedDwords()
61 TII->isReductionOp(MI->getOpcode())) in OccupiedDwords()
75 if (TII->isALUInstr(MI->getOpcode())) in isALU()
77 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) in isALU()
122 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4) in SubstituteKCacheBank()
126 TII->getSrcs(MI); in SubstituteKCacheBank()
127 assert((TII->isALUInstr(MI->getOpcode()) || in SubstituteKCacheBank()
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DR600ClauseMergePass.cpp48 const R600InstrInfo *TII; member in __anon4f803f610111::R600ClauseMergePass
77 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm(); in getCFAluSize()
83 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm(); in isCFAluEnabled()
88 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in cleanPotentialDisabledCFAlu()
107 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in mergeIfPossible()
111 if (CumuledInsts >= TII->getMaxAlusPerClause()) { in mergeIfPossible()
119 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0); in mergeIfPossible()
121 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0); in mergeIfPossible()
123 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0); in mergeIfPossible()
135 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1); in mergeIfPossible()
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DSIFoldOperands.cpp142 const SIInstrInfo *TII) { in tryAddToFoldList() argument
143 if (!TII->isOperandLegal(MI, OpNo, OpToFold)) { in tryAddToFoldList()
151 MI->setDesc(TII->get(AMDGPU::V_MAD_F32)); in tryAddToFoldList()
152 bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII); in tryAddToFoldList()
157 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
170 bool CanCommute = TII->findCommutedOpIndices(MI, CommuteIdx0, CommuteIdx1); in tryAddToFoldList()
188 !TII->commuteInstruction(MI, false, CommuteIdx0, CommuteIdx1)) in tryAddToFoldList()
191 if (!TII->isOperandLegal(MI, OpNo, OpToFold)) in tryAddToFoldList()
203 const SIInstrInfo *TII, const SIRegisterInfo &TRI, in foldOperand() argument
225 const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode()); in foldOperand()
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/external/llvm/lib/Target/XCore/
DXCoreFrameLowering.cpp64 const TargetInstrInfo &TII, in EmitDefCfaRegister() argument
68 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
74 const TargetInstrInfo &TII, in EmitDefCfaOffset() argument
78 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaOffset()
84 const TargetInstrInfo &TII, MachineModuleInfo *MMI, in EmitCfiOffset() argument
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitCfiOffset()
100 const TargetInstrInfo &TII, MachineModuleInfo *MMI, in IfNeededExtSP() argument
108 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
111 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4); in IfNeededExtSP()
124 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededLDAWSP() argument
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DXCoreRegisterInfo.cpp63 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
94 const XCoreInstrInfo &TII, in InsertFPConstInst() argument
103 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
130 const XCoreInstrInfo &TII, in InsertSPImmInst() argument
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/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp72 const HexagonInstrInfo *TII = QST.getInstrInfo(); in runOnMachineFunction() local
107 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
111 TII->get(Opcode)); in runOnMachineFunction()
150 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
154 TII->get(Opcode)); in runOnMachineFunction()
191 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
195 TII->get(Opcode)); in runOnMachineFunction()
228 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
232 TII->get(Opcode)); in runOnMachineFunction()
252 if (!TII->isValidOffset(Hexagon::S2_storeri_io, Offset)) { in runOnMachineFunction()
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DHexagonCopyToCombine.cpp60 const HexagonInstrInfo *TII; member in __anon0e9826260111::HexagonCopyToCombine
115 const HexagonInstrInfo *TII, in isCombinableInstType() argument
348 if(TII->mayBeNewStore(MI)) { in findPotentialNewifiableTFRs()
363 if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively)) in findPotentialNewifiableTFRs()
406 TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); in runOnMachineFunction()
429 if (!isCombinableInstType(I1, TII, ShouldCombineAggressively)) in runOnMachineFunction()
462 if (!isCombinableInstType(I2, TII, ShouldCombineAggressively)) in findPairable()
551 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
558 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
567 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
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/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp170 const MipsInstrInfo *TII = in initMBBInfo() local
178 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI); in initMBBInfo()
217 const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>( in replaceBranch() local
219 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch()
220 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
261 const MipsInstrInfo *TII = in expandToLongBranch() local
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
297 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
316 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
319 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) in expandToLongBranch()
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DMipsSEFrameLowering.cpp76 const MipsSEInstrInfo &TII; member in __anon82167c930111::ExpandPseudo
84 TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())), in ExpandPseudo()
160 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
161 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
175 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
177 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
196 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); in expandLoadACC()
198 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
200 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
221 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
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/external/llvm/lib/Target/ARM/
DARMFrameLowering.cpp102 const ARMBaseInstrInfo &TII, in isCSRestore() argument
125 const ARMBaseInstrInfo &TII, unsigned DestReg, in emitRegPlusImmediate() argument
132 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
135 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
140 const ARMBaseInstrInfo &TII, int NumBytes, in emitSPUpdate() argument
144 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
209 DebugLoc dl, const ARMBaseInstrInfo &TII, bool HasFP) { in emitDefCFAOffsets()
219 TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitDefCFAOffsets()
235 const TargetInstrInfo &TII, in emitAligningInstructions() argument
258 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
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DThumb1FrameLowering.cpp44 const TargetInstrInfo &TII, DebugLoc dl, in emitSPUpdate() argument
47 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitSPUpdate()
55 const Thumb1InstrInfo &TII = in eliminateCallFramePseudoInstr() local
76 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
79 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
95 const Thumb1InstrInfo &TII = in emitPrologue() local
122 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
127 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
134 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), in emitPrologue()
139 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
[all …]
DThumbRegisterInfo.cpp70 const TargetInstrInfo &TII = *STI.getInstrInfo(); in emitThumb1LoadConstPool() local
76 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) in emitThumb1LoadConstPool()
89 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitThumb2LoadConstPool() local
95 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci)) in emitThumb2LoadConstPool()
129 const TargetInstrInfo &TII, in emitThumbRegPlusImmInReg() argument
151 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) in emitThumbRegPlusImmInReg()
154 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) in emitThumbRegPlusImmInReg()
156 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)) in emitThumbRegPlusImmInReg()
166 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg()
184 int NumBytes, const TargetInstrInfo &TII, in emitThumbRegPlusImmediate() argument
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/external/llvm/lib/Target/MSP430/
DMSP430FrameLowering.cpp47 const MSP430InstrInfo &TII = in emitPrologue() local
68 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
72 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) in emitPrologue()
100 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
112 const MSP430InstrInfo &TII = in emitEpilogue() local
137 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); in emitEpilogue()
159 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); in emitEpilogue()
163 TII.get(MSP430::SUB16ri), MSP430::SP) in emitEpilogue()
172 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) in emitEpilogue()
193 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in spillCalleeSavedRegisters() local
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/external/llvm/lib/Target/AArch64/
DAArch64A53Fix835769.cpp82 const TargetInstrInfo *TII; member in __anonfcea26df0111::AArch64A53Fix835769
112 TII = F.getSubtarget().getInstrInfo(); in runOnMachineFunction()
123 const TargetInstrInfo *TII) { in getBBFallenThrough() argument
136 if (S == PrevBB && !TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond) && in getBBFallenThrough()
148 const TargetInstrInfo *TII) { in getLastNonPseudo() argument
153 while ((FMBB = getBBFallenThrough(FMBB, TII))) { in getLastNonPseudo()
164 const TargetInstrInfo *TII) { in insertNopBeforeInstruction() argument
168 MachineInstr *I = getLastNonPseudo(MBB, TII); in insertNopBeforeInstruction()
171 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0); in insertNopBeforeInstruction()
175 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0); in insertNopBeforeInstruction()
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DAArch64ExpandPseudoInsts.cpp39 const AArch64InstrInfo *TII; member in __anon3d2962aa0111::AArch64ExpandPseudo
102 const AArch64InstrInfo *TII, unsigned ChunkIdx) { in tryOrrMovk() argument
110 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)) in tryOrrMovk()
120 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in tryOrrMovk()
153 const AArch64InstrInfo *TII) { in tryToreplicateChunks() argument
177 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)) in tryToreplicateChunks()
197 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in tryToreplicateChunks()
222 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in tryToreplicateChunks()
287 const AArch64InstrInfo *TII) { in trySequenceOfOnes() argument
360 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)) in trySequenceOfOnes()
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/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp42 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) { in X86FrameLowering()
270 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg) in emitSPUpdate()
275 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
294 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
348 TII.get(getLEArOpcode(Uses64BitFramePtr)), in BuildStackAdjustment()
356 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in BuildStackAdjustment()
400 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in BuildCFI()
492 const TargetInstrInfo &TII = *STI.getInstrInfo(); in emitStackProbeInline() local
581 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInline()
584 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInline()
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/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp331 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in lowerDynamicAlloc() local
359 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
363 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) in lowerDynamicAlloc()
367 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
384 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in lowerDynamicAlloc()
389 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) in lowerDynamicAlloc()
395 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
399 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
409 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) in lowerDynamicAlloc()
414 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) in lowerDynamicAlloc()
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DPPCBranchSelector.cpp67 const PPCInstrInfo *TII = in runOnMachineFunction() local
74 [TII](MachineBasicBlock &MBB, unsigned Offset) -> unsigned { in runOnMachineFunction()
107 BlockSize += TII->GetInstSizeInBytes(MBBI); in runOnMachineFunction()
154 MBBStartOffset += TII->GetInstSizeInBytes(I); in runOnMachineFunction()
197 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) in runOnMachineFunction()
201 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2); in runOnMachineFunction()
204 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2); in runOnMachineFunction()
206 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); in runOnMachineFunction()
208 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); in runOnMachineFunction()
210 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); in runOnMachineFunction()
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/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp124 const TargetInstrInfo *TII; member in __anon2734e12b0111::PeepholeOptimizer
313 const TargetInstrInfo *TII; member in __anon2734e12b0111::ValueTracker
353 const TargetInstrInfo *TII = nullptr) in ValueTracker() argument
355 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
372 const TargetInstrInfo *TII = nullptr) in ValueTracker() argument
374 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
416 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
542 TII->get(TargetOpcode::COPY), NewVR) in INITIALIZE_PASS_DEPENDENCY()
568 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
574 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
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