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Searched refs:TRI (Results 1 – 25 of 307) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DLivePhysRegs.h44 const TargetRegisterInfo *TRI; variable
51 LivePhysRegs() : TRI(nullptr), LiveRegs() {} in LivePhysRegs()
54 LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) { in LivePhysRegs() argument
55 assert(TRI && "Invalid TargetRegisterInfo pointer."); in LivePhysRegs()
56 LiveRegs.setUniverse(TRI->getNumRegs()); in LivePhysRegs()
60 void init(const TargetRegisterInfo *TRI) { in init() argument
61 assert(TRI && "Invalid TargetRegisterInfo pointer."); in init()
62 this->TRI = TRI; in init()
64 LiveRegs.setUniverse(TRI->getNumRegs()); in init()
75 assert(TRI && "LivePhysRegs is not initialized."); in addReg()
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DMachineInstr.h844 const TargetRegisterInfo *TRI = nullptr) const {
845 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
865 const TargetRegisterInfo *TRI = nullptr) const {
866 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
874 const TargetRegisterInfo *TRI = nullptr) const {
875 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
881 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
882 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
889 const TargetRegisterInfo *TRI = nullptr) const {
890 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
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/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp115 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { in hasVGPROperands() argument
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
130 const SIRegisterInfo &TRI, in getCopyRegClasses() argument
138 TRI.getPhysRegClass(SrcReg); in getCopyRegClasses()
146 TRI.getPhysRegClass(DstReg); in getCopyRegClasses()
153 const SIRegisterInfo &TRI) { in isVGPRToSGPRCopy() argument
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
159 const SIRegisterInfo &TRI) { in isSGPRToVGPRCopy() argument
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
177 const SIRegisterInfo *TRI, in foldVGPRCopyIntoRegSequence() argument
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DR600ExpandSpecialInstrs.cpp71 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
179 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
200 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
203 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
206 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
231 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
286 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction()
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DSIFrameLowering.cpp68 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in emitPrologue() local
78 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue( in emitPrologue()
83 PreloadedPrivateBufferReg = TRI->getPreloadedValue( in emitPrologue()
118 if (ScratchRsrcReg == TRI->reservedPrivateSegmentBufferReg(MF)) { in emitPrologue()
137 if (ScratchWaveOffsetReg == TRI->reservedPrivateSegmentWaveByteOffsetReg(MF)) { in emitPrologue()
147 !TRI->isSubRegisterEq(ScratchRsrcReg, Reg)); in emitPrologue()
158 assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg)); in emitPrologue()
174 !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchRsrcReg) && in emitPrologue()
175 !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchWaveOffsetReg)); in emitPrologue()
177 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitPrologue()
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DSIMachineFunctionInfo.cpp113 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer() argument
114 PrivateSegmentBufferUserSGPR = TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
120 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr() argument
121 DispatchPtrUserSGPR = TRI.getMatchingSuperReg( in addDispatchPtr()
127 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr() argument
128 QueuePtrUserSGPR = TRI.getMatchingSuperReg( in addQueuePtr()
134 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr() argument
135 KernargSegmentPtrUserSGPR = TRI.getMatchingSuperReg( in addKernargSegmentPtr()
146 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( in getSpilledReg() local
158 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass); in getSpilledReg()
DSIShrinkInstructions.cpp75 static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI, in isVGPR() argument
81 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg())); in isVGPR()
83 return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg())); in isVGPR()
87 const SIRegisterInfo &TRI, in canShrink() argument
102 if (!isVGPR(Src2, TRI, MRI) || in canShrink()
116 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0))) in canShrink()
146 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in foldImmediates() local
159 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)) in foldImmediates()
208 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
235 if (!canShrink(MI, TII, TRI, MRI)) { in runOnMachineFunction()
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/external/llvm/lib/CodeGen/
DRegisterClassInfo.cpp33 : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {} in RegisterClassInfo()
40 if (MF->getSubtarget().getRegisterInfo() != TRI) { in runOnMachineFunction()
41 TRI = MF->getSubtarget().getRegisterInfo(); in runOnMachineFunction()
42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
43 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction()
50 assert(TRI && "no register info set"); in runOnMachineFunction()
51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction()
56 CSRNum.resize(TRI->getNumRegs(), 0); in runOnMachineFunction()
58 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
103 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
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DTargetRegisterInfo.cpp45 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, in PrintReg() argument
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { in PrintReg()
54 else if (TRI && Reg < TRI->getNumRegs()) in PrintReg()
55 OS << '%' << TRI->getName(Reg); in PrintReg()
59 if (TRI) in PrintReg()
60 OS << ':' << TRI->getSubRegIndexName(SubIdx); in PrintReg()
67 Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { in PrintRegUnit() argument
68 return Printable([Unit, TRI](raw_ostream &OS) { in PrintRegUnit()
70 if (!TRI) { in PrintRegUnit()
76 if (Unit >= TRI->getNumRegUnits()) { in PrintRegUnit()
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DLiveRegMatrix.cpp50 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction()
54 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction()
74 bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, in foreachUnit() argument
77 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
99 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign()
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign()
105 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); in assign()
116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
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DAggressiveAntiDepBreaker.cpp118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in AggressiveAntiDepBreaker()
123 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
133 dbgs() << " " << TRI->getName(r)); in AggressiveAntiDepBreaker()
143 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); in StartBlock()
153 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
166 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { in StartBlock()
169 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
197 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
206 dbgs() << " " << TRI->getName(Reg) << "=g" << in Observe()
244 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs()
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DRegisterScavenging.cpp35 for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) { in setRegUsed()
69 TRI = MF.getSubtarget().getRegisterInfo(); in enterBasicBlock()
72 assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) && in enterBasicBlock()
82 NumRegUnits = TRI->getNumRegUnits(); in enterBasicBlock()
96 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
115 for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) { in determineKillsAndDefs()
116 for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) { in determineKillsAndDefs()
217 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in forward()
223 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { in forward()
242 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && in forward()
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DStackMaps.cpp78 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) { in getDwarfRegNum() argument
79 int RegNum = TRI->getDwarfRegNum(Reg, false); in getDwarfRegNum()
80 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR) in getDwarfRegNum()
81 RegNum = TRI->getDwarfRegNum(*SR, false); in getDwarfRegNum()
91 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo(); in parseOperand() local
105 getDwarfRegNum(Reg, TRI), Imm); in parseOperand()
114 getDwarfRegNum(Reg, TRI), Imm); in parseOperand()
139 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); in parseOperand()
143 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI); in parseOperand()
144 unsigned LLVMRegNum = TRI->getLLVMRegNum(DwarfRegNum, false); in parseOperand()
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DCriticalAntiDepBreaker.cpp34 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
35 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker()
36 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {} in CriticalAntiDepBreaker()
43 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { in StartBlock()
61 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
74 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { in StartBlock()
76 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { in StartBlock()
103 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
180 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); in PrescanInstruction()
190 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) { in PrescanInstruction()
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DMIRPrinter.cpp80 const TargetRegisterInfo *TRI);
90 const TargetRegisterInfo *TRI);
120 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
124 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
147 const TargetRegisterInfo *TRI) { in printReg() argument
153 else if (Reg < TRI->getNumRegs()) in printReg()
154 OS << '%' << StringRef(TRI->getName(Reg)).lower(); in printReg()
160 const TargetRegisterInfo *TRI) { in printReg() argument
162 printReg(Reg, OS, TRI); in printReg()
199 const TargetRegisterInfo *TRI) { in convert() argument
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DMachineCopyPropagation.cpp37 const TargetRegisterInfo *TRI; member in __anonadbeb66a0111::MachineCopyPropagation
69 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in SourceNoLongerAvailable()
78 for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR) in SourceNoLongerAvailable()
114 const TargetRegisterInfo *TRI) { in isNopCopy() argument
118 if (TRI->isSubRegister(SrcSrc, Def)) { in isNopCopy()
120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy()
123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); in isNopCopy()
156 isNopCopy(CopyMI, Def, Src, TRI)) { in CopyPropagateBlock()
176 I->clearRegisterKills(Def, TRI); in CopyPropagateBlock()
186 for (MCRegAliasIterator AI(Src, TRI, true); AI.isValid(); ++AI) { in CopyPropagateBlock()
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DLiveVariables.cpp197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef()
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
274 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in HandlePhysRegUse()
290 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastRefOrPartRef()
339 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegKill()
353 for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true); SS.isValid(); in HandlePhysRegKill()
369 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); in HandlePhysRegKill()
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DRegisterPressure.cpp45 const TargetRegisterInfo *TRI) { in dumpRegSetPressure() argument
49 dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << '\n'; in dumpRegSetPressure()
58 void RegisterPressure::dump(const TargetRegisterInfo *TRI) const { in dump()
60 dumpRegSetPressure(MaxSetPressure, TRI); in dump()
63 dbgs() << PrintVRegOrUnit(Reg, TRI) << " "; in dump()
67 dbgs() << PrintVRegOrUnit(Reg, TRI) << " "; in dump()
75 dumpRegSetPressure(CurrSetPressure, TRI); in dump()
77 P.dump(TRI); in dump()
80 void PressureDiff::dump(const TargetRegisterInfo &TRI) const { in dump()
85 dbgs() << sep << TRI.getRegPressureSetName(Change.getPSet()) in dump()
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DRegAllocFast.cpp58 const TargetRegisterInfo *TRI; member in __anonb64cd7cd0111::RAFast
125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in isRegUsedInInstr()
240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); in addKillFlag()
285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI) in spillVirtReg()
286 << " in " << PrintReg(LR.PhysReg, TRI)); in spillVirtReg()
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); in spillVirtReg()
365 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { in usePhysReg()
380 assert((TRI->isSuperRegister(PhysReg, Alias) || in usePhysReg()
381 TRI->isSuperRegister(Alias, PhysReg)) && in usePhysReg()
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DInterferenceCache.cpp36 if (PhysRegEntriesCount == TRI->getNumRegs()) return; in reinitPhysRegEntries()
38 PhysRegEntriesCount = TRI->getNumRegs(); in reinitPhysRegEntries()
50 TRI = tri; in init()
59 if (!Entries[E].valid(LIUArray, TRI)) in get()
60 Entries[E].revalidate(LIUArray, TRI); in get()
74 Entries[E].reset(PhysReg, LIUArray, TRI, MF); in get()
83 const TargetRegisterInfo *TRI) { in revalidate() argument
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) in revalidate()
95 const TargetRegisterInfo *TRI, in reset() argument
106 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in reset()
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/external/llvm/lib/Target/Mips/
DMipsOptionRecord.h45 const MCRegisterInfo *TRI = Context.getRegisterInfo(); in MipsRegInfoRecord() local
46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
52 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
53 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
54 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
DMipsFrameLowering.cpp98 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasFP() local
102 TRI->needsStackRealignment(MF); in hasFP()
107 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasBP() local
109 return MFI->hasVarSizedObjects() && TRI->needsStackRealignment(MF); in hasBP()
114 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); in estimateStackSize() local
123 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) { in estimateStackSize()
124 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize(); in estimateStackSize()
/external/mesa3d/src/gallium/drivers/radeon/
DR600ExpandSpecialInstrs.cpp53 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction()
106 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
107 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction()
111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction()
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction()
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
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/external/llvm/lib/CodeGen/AsmPrinter/
DDwarfExpression.cpp76 int DwarfReg = TRI.getDwarfRegNum(MachineReg, false); in AddMachineRegIndirect()
87 if (!TRI.isPhysicalRegister(MachineReg)) in AddMachineRegPiece()
90 int Reg = TRI.getDwarfRegNum(MachineReg, false); in AddMachineRegPiece()
102 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { in AddMachineRegPiece()
103 Reg = TRI.getDwarfRegNum(*SR, false); in AddMachineRegPiece()
105 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); in AddMachineRegPiece()
106 unsigned Size = TRI.getSubRegIdxSize(Idx); in AddMachineRegPiece()
107 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); in AddMachineRegPiece()
131 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; in AddMachineRegPiece()
135 for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { in AddMachineRegPiece()
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/external/eigen/test/
Dproduct_trsolve.cpp12 #define VERIFY_TRSM(TRI,XB) { \ argument
14 (TRI).solveInPlace(XB); \
15 VERIFY_IS_APPROX((TRI).toDenseMatrix() * (XB), ref); \
17 (XB) = (TRI).solve(XB); \
18 VERIFY_IS_APPROX((TRI).toDenseMatrix() * (XB), ref); \
21 #define VERIFY_TRSM_ONTHERIGHT(TRI,XB) { \ argument
23 (TRI).transpose().template solveInPlace<OnTheRight>(XB.transpose()); \
24 VERIFY_IS_APPROX((XB).transpose() * (TRI).transpose().toDenseMatrix(), ref.transpose()); \
26 (XB).transpose() = (TRI).transpose().template solve<OnTheRight>(XB.transpose()); \
27 VERIFY_IS_APPROX((XB).transpose() * (TRI).transpose().toDenseMatrix(), ref.transpose()); \

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