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Searched refs:fcsel (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Dfast-isel-select.ll48 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne
56 ; CHECK-NEXT: fcsel {{d[0-9]+}}, d0, d1, ne
73 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, gt
82 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ge
91 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, mi
100 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ls
109 ; CHECK-NEXT: fcsel [[REG:s[0-9]+]], s2, s3, mi
110 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, [[REG]], gt
119 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vc
128 ; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vs
[all …]
Darm64-fcmp-opt.ll46 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], eq
58 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], gt
70 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ge
82 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], mi
94 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ls
106 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vc
117 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vs
128 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], hi
139 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], pl
150 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], lt
[all …]
Ddirectcond.ll26 ; CHECK-NEXT: fcsel s0, s0, s1, ne
27 ; CHECK-NOFP-NOT: fcsel
35 ; CHECK-NEXT: fcsel d0, d0, d1, ne
36 ; CHECK-NOFP-NOT: fcsel
Darm64-fmax.ll36 ; results. Make sure they're put back before we resort to the normal fcsel.
45 ; CHECK: fcsel s0, s1, s0, ne
63 ; CHECK: fcsel
Dfp-cond-sel.ll17 ; CHECK: fcsel {{s[0-9]+}}, s[[FLT0]], s[[FLT1]], hi
25 ; CHECK: fcsel {{d[0-9]+}}, d[[FLT1]], d[[FLT0]], le
Dregress-f128csel-flags.ll20 ; It's also reasonably important that the actual fcsel comes before the
23 ; CHECK: fcsel {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, ne
Darm64-regress-f128csel-flags.ll20 ; It's also reasonably important that the actual fcsel comes before the
23 ; CHECK: fcsel {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, ne
Darm64-fmax-safe.ll36 ; results. Make sure they're put back before we resort to the normal fcsel.
45 ; CHECK: fcsel s0, s1, s0, ne
Darm64-fp.ll5 ; CHECK: fcsel s0, s0, s1, ne
Df16-instructions.ll121 ; CHECK-NEXT: fcsel s0, s0, s1, ne
137 ; CHECK-NEXT: fcsel s0, s0, s1, ne
150 ; CHECK-NEXT: fcsel s0, s0, s1, ne
164 ; CHECK-NEXT: fcsel s0, s0, s1, ne
/external/llvm/test/MC/AArch64/
Darm64-nv-cond.s3 fcsel d28,d31,d31,nv label
Darm64-fp-encoding.s226 fcsel h1, h2, h3, eq
227 fcsel s1, s2, s3, eq
228 fcsel d1, d2, d3, eq define
230 ; FP16: fcsel h1, h2, h3, eq ; encoding: [0x41,0x0c,0xe3,0x1e]
232 ; NO-FP16-NEXT: fcsel h1, h2, h3, eq
233 ; CHECK: fcsel s1, s2, s3, eq ; encoding: [0x41,0x0c,0x23,0x1e]
234 ; CHECK: fcsel d1, d2, d3, eq ; encoding: [0x41,0x0c,0x63,0x1e]
Dbasic-a64-diagnostics.s1600 fcsel q3, q20, q9, pl
1601 fcsel h9, h10, h11, mi
1602 fcsel b9, b10, b11, mi
Dbasic-a64-instructions.s1818 fcsel s3, s20, s9, pl
1819 fcsel d9, d10, d11, mi define
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt184 # FP16: fcsel h1, h2, h3, eq
185 # CHECK: fcsel s1, s2, s3, eq
186 # CHECK: fcsel d1, d2, d3, eq
Dbasic-a64-instructions.txt1384 # CHECK: fcsel s3, s20, s9, pl
1385 # CHECK: fcsel d9, d10, d11, mi
/external/valgrind/docs/internals/
DMERGE_3_10_1.txt164 //340856 disInstr(arm64): unhandled instruction 0x1E634C45 (fcsel)
/external/v8/test/cctest/
Dtest-disasm-arm64.cc1495 COMPARE(fcsel(s0, s1, s2, eq), "fcsel s0, s1, s2, eq") in TEST_()
1496 COMPARE(fcsel(s31, s31, s30, ne), "fcsel s31, s31, s30, ne"); in TEST_()
1497 COMPARE(fcsel(d0, d1, d2, mi), "fcsel d0, d1, d2, mi"); in TEST_()
1498 COMPARE(fcsel(d31, d30, d31, pl), "fcsel d31, d30, d31, pl"); in TEST_()
1499 COMPARE(fcsel(s14, s15, s16, al), "fcsel s14, s15, s16, al"); in TEST_()
1500 COMPARE(fcsel(d17, d18, d19, nv), "fcsel d17, d18, d19, nv"); in TEST_()
Dtest-assembler-arm64.cc6065 TEST(fcsel) { in TEST() argument
6081 __ fcsel(s4, s16, s17, al); in TEST() local
6082 __ fcsel(d5, d18, d19, nv); in TEST() local
/external/vixl/test/
Dtest-disasm-a64.cc2419 COMPARE(fcsel(s0, s1, s2, eq), "fcsel s0, s1, s2, eq") in TEST()
2420 COMPARE(fcsel(s31, s31, s30, ne), "fcsel s31, s31, s30, ne"); in TEST()
2421 COMPARE(fcsel(d0, d1, d2, mi), "fcsel d0, d1, d2, mi"); in TEST()
2422 COMPARE(fcsel(d31, d30, d31, pl), "fcsel d31, d30, d31, pl"); in TEST()
2423 COMPARE(fcsel(s14, s15, s16, al), "fcsel s14, s15, s16, al"); in TEST()
2424 COMPARE(fcsel(d17, d18, d19, nv), "fcsel d17, d18, d19, nv"); in TEST()
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h591 fcsel(fd, fn, fm, cond); in Fcsel()
Dassembler-arm64.h1568 void fcsel(const FPRegister& fd,
Dassembler-arm64.cc1949 void Assembler::fcsel(const FPRegister& fd, in fcsel() function in v8::internal::Assembler
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h1184 fcsel(vd, vn, vm, cond); in Fcsel()
Dassembler-a64.h2157 void fcsel(const VRegister& vd,

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