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Searched refs:isV9 (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcMCAsmInfo.cpp24 bool isV9 = (TheTriple.getArch() == Triple::sparcv9); in SparcELFMCAsmInfo() local
27 if (isV9) { in SparcELFMCAsmInfo()
34 Data64bitsDirective = (isV9) ? "\t.xword\t" : nullptr; in SparcELFMCAsmInfo()
/external/llvm/lib/Target/Sparc/InstPrinter/
DSparcInstPrinter.cpp37 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { in isV9() function in SparcInstPrinter
84 if (isV9(STI) in printSparcAliasInstr()
DSparcInstPrinter.h35 bool isV9(const MCSubtargetInfo &STI) const;
/external/llvm/lib/Target/Sparc/
DSparcSubtarget.h65 bool isV9() const { return IsV9; } in isV9() function
DSparcRegisterInfo.cpp91 if (!Subtarget.isV9()) { in getReservedRegs()
183 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
DSparcInstrInfo.cpp308 if (Subtarget.isV9()) { in copyPhysReg()
318 if (Subtarget.isV9()) { in copyPhysReg()
DDelaySlotFiller.cpp127 if (!Subtarget->isV9() && in runOnMachineBasicBlock()
DSparcISelLowering.cpp1594 (Subtarget->isV9() ? Legal: Expand)); in SparcTargetLowering()
1610 if (!Subtarget->isV9()) { in SparcTargetLowering()
1686 if (Subtarget->isV9() && Subtarget->hasHardQuad()) { in SparcTargetLowering()
1702 if (Subtarget->isV9()) { in SparcTargetLowering()
2779 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { in LowerFNEGorFABS() argument
2797 if (isV9) in LowerFNEGorFABS()
2921 bool isV9 = Subtarget->isV9(); in LowerOperation() local
2964 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
DSparcInstrInfo.td32 def HasV9 : Predicate<"Subtarget->isV9()">,
38 def HasNoV9 : Predicate<"!Subtarget->isV9()">;
/external/llvm/docs/
DWritingAnLLVMBackend.rst1434 if (TM.getSubtarget<SparcSubtarget>().isV9())