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Searched refs:v4i8 (Results 1 – 25 of 50) sorted by relevance

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/external/clang/test/CodeGen/
Dbuiltins-mips.c10 typedef signed char v4i8 __attribute__ ((vector_size(4))); typedef
19 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; in foo()
27 v4i8_a = (v4i8) {1, 2, 3, 0xFF}; in foo()
28 v4i8_b = (v4i8) {2, 4, 6, 8}; in foo()
91 v4i8_a = (v4i8) {1, 2, 3, 4}; in foo()
124 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; in foo()
142 v4i8_a = (v4i8) {1, 2, 3, 4}; in foo()
145 v4i8_a = (v4i8) {128, 64, 32, 16}; in foo()
168 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; in foo()
211 v4i8_b = (v4i8) {1, 2, 3, 4}; in foo()
[all …]
Dsystemz-abi-vector.c15 typedef __attribute__((vector_size(4))) char v4i8; typedef
50 v4i8 pass_v4i8(v4i8 arg) { return arg; } in pass_v4i8()
143 struct agg_v4i8 { v4i8 a; };
166 struct agg_novector1 { v4i8 a; v4i8 b; };
171 struct agg_novector2 { v4i8 a; float b; };
176 struct agg_novector3 { v4i8 a; int : 0; };
181 struct agg_novector4 { v4i8 a __attribute__((aligned (8))); };
253 v4i8 va_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, v4i8); } in va_v4i8()
/external/llvm/test/CodeGen/AArch64/
Dneon-truncStore-extLoad.ll34 define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
35 ; CHECK-LABEL: loadSExt.v4i8:
42 define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
43 ; CHECK-LABEL: loadZExt.v4i8:
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td17 def V4I8: PatLeaf<(v4i8 IntRegs:$R)>;
67 defm : bitconvert_32<v4i8, i32>;
69 defm : bitconvert_32<v2i16, v4i8>;
138 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
302 // Adds two v4i8: Hexagon does not have an insn for this one, so we
304 def: Pat<(v4i8 (add (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
307 // Subtract two v4i8: Hexagon does not have an insn for this one, so we
309 def: Pat<(v4i8 (sub (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
315 def: Pat<(v4i8 (select I1:$Pu, V4I8:$Rs, V4I8:$Rt)),
377 def: Pat<(v4i8 (trunc V4I16:$Rs)),
[all …]
DHexagonRegisterInfo.td203 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
239 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp594 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, in getCastInstrCost()
621 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
622 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
628 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, in getCastInstrCost()
652 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, in getCastInstrCost()
653 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, in getCastInstrCost()
659 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, in getCastInstrCost()
672 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
676 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, in getCastInstrCost()
685 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, in getCastInstrCost()
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/external/llvm/include/llvm/CodeGen/
DMachineValueType.h70 v4i8 = 23, // 4 x i8 enumerator
227 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 || in is32BitVector()
320 case v4i8: in getVectorElementType()
397 case v4i8: in getVectorNumElements()
455 case v4i8: in getSizeInBits()
598 if (NumElements == 4) return MVT::v4i8; in getVectorVT()
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1313 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1315 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1319 def : DSPPat<(v4i8 (load addr:$a)),
1320 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1323 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1337 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1338 def : DSPBinPat<ADDU_QB, v4i8, add>;
1339 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1340 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1357 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
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/external/llvm/test/CodeGen/ARM/
D2012-08-23-legalize-vmull.ll13 ; v4i8
54 ; v4i8
104 ; v4i8 x v4i16
Dcttz_vector.ll7 declare <4 x i8> @llvm.cttz.v4i8(<4 x i8>, i1)
44 %tmp = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %a, i1 false)
228 %tmp = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %a, i1 true)
/external/llvm/test/CodeGen/SystemZ/
Dvec-const-01.ll73 ; Test an all-zeros v4i8 that gets promoted to v16i8.
81 ; Test a mixed v4i8 that gets promoted to v16i8 (mask 0x9000).
Dvec-move-01.ll61 ; Test v4i8 moves.
Dvec-move-16.ll40 ; Test a v4i8->v4i32 extension.
Dvec-move-15.ll40 ; Test a v4i8->v4i32 extension.
Dvec-and-03.ll49 ; Test a v4i8->v4i32 extension.
Dvec-move-17.ll40 ; Test a v4i32->v4i8 truncation. At the moment we use a VPERM rather than
/external/llvm/test/CodeGen/X86/
D2011-12-8-bitcastintprom.ll3 ; Make sure that the conversion between v4i8 to v2i16 is not a simple bitcast.
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
233 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
273 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
275 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1887 "llvm.nvvm.suld.1d.v4i8.clamp">;
1932 "llvm.nvvm.suld.1d.array.v4i8.clamp">;
1977 "llvm.nvvm.suld.2d.v4i8.clamp">;
2022 "llvm.nvvm.suld.2d.array.v4i8.clamp">;
2067 "llvm.nvvm.suld.3d.v4i8.clamp">;
2113 "llvm.nvvm.suld.1d.v4i8.trap">;
2158 "llvm.nvvm.suld.1d.array.v4i8.trap">;
2203 "llvm.nvvm.suld.2d.v4i8.trap">;
2248 "llvm.nvvm.suld.2d.array.v4i8.trap">;
2293 "llvm.nvvm.suld.3d.v4i8.trap">;
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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp114 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
115 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
129 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
130 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-illegal-type.ll4 ; Used to fail with "Cannot select: ch = store x,x,x,<ST4[undef](align=8), trunc to v4i8>"
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp58 (int)MVT::v4i8, in InitAMDILLowering()
86 (int)MVT::v4i8, in InitAMDILLowering()
208 setOperationAction(ISD::UDIV, MVT::v4i8, Expand); in InitAMDILLowering()
650 } else if (OVT == MVT::v4i8) { in LowerSREM8()
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td49 // Extract v4i8
54 (v4i8 V4I8Regs:$src), imm:$c))],
115 // Insert v4i8
792 def : Pat<(v4i8 (vec_shuf:$op V4I8Regs:$src1, V4I8Regs:$src2)),
1253 // v4i8 -> i32
1277 // i32 -> v4i8
1305 // v4i8 -> v2i16
1315 // v2i16 -> v4i8
1316 def : Pat<(v4i8 (bitconvert V2I16Regs:$s)),
1351 // f32 -> v4i8
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/external/llvm/lib/IR/
DValueTypes.cpp150 case MVT::v4i8: return "v4i8"; in getEVTString()
228 case MVT::v4i8: return VectorType::get(Type::getInt8Ty(Context), 4); in getTypeForEVT()
/external/llvm/test/Analysis/CostModel/X86/
Dcast.ll78 %C.v4i8.z = zext <4 x i8> undef to <4 x i64>
81 %C.v4i8.s = sext <4 x i8> undef to <4 x i64>

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