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Searched refs:ImmOp (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonOptAddrMode.cpp90 bool changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
92 bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum);
94 const MachineOperand &ImmOp, unsigned ImmOpNum);
304 bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, in changeLoad() argument
323 MIB.addOperand(ImmOp); in changeLoad()
331 const GlobalValue *GV = ImmOp.getGlobal(); in changeLoad()
332 int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(2).getImm(); in changeLoad()
334 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
348 MIB.addOperand(ImmOp); in changeLoad()
362 bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, in changeStore() argument
[all …]
DHexagonInstrInfoV4.td1260 Operand ImmOp, bits<2>MajOp>
1262 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1342 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1345 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1411 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1413 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1422 string ImmOpStr = !cast<string>(ImmOp);
1444 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1448 ImmOp:$offset, IntRegs:$src3),
1459 string ImmOpStr = !cast<string>(ImmOp);
[all …]
DHexagonInstrInfoV60.td121 class T_vstore_ai <string mnemonic, string baseOp, Operand ImmOp,
123 : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
161 class T_vstore_new_ai <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
162 : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
190 class T_vstore_pred_ai <string mnemonic, string baseOp, Operand ImmOp,
193 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
252 class T_vstore_qpred_ai <Operand ImmOp, RegisterClass RC,
255 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
291 class T_vstore_new_pred_ai <string baseOp, Operand ImmOp, RegisterClass RC,
294 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
[all …]
DHexagonInstrInfo.td68 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
70 (ins IntRegs:$src1, ImmOp:$src2),
1638 Operand ImmOp>
1639 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1647 string ImmOpStr = !cast<string>(ImmOp);
1670 Operand ImmOp, bit isNot, bit isPredNew>
1672 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1682 string ImmOpStr = !cast<string>(ImmOp);
1712 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1715 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
[all …]
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
DR600MCCodeEmitter.cpp250 MCOperand ImmOp = MI.getOperand(ImmOpIndex); in EmitSrc() local
251 if (ImmOp.isFPImm()) { in EmitSrc()
252 Value.f = ImmOp.getFPImm(); in EmitSrc()
254 assert(ImmOp.isImm()); in EmitSrc()
255 Value.i = ImmOp.getImm(); in EmitSrc()
/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp385 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteFrameIndex() local
392 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteFrameIndex()
409 ImmOp.ChangeToImmediate(0); in rewriteFrameIndex()
413 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteFrameIndex()
DThumb2InstrInfo.cpp595 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1); in rewriteT2FrameIndex() local
611 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteT2FrameIndex()
629 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteT2FrameIndex()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb1RegisterInfo.cpp493 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteFrameIndex() local
500 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteFrameIndex()
517 ImmOp.ChangeToImmediate(0); in rewriteFrameIndex()
521 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteFrameIndex()
DThumb2InstrInfo.cpp521 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1); in rewriteT2FrameIndex() local
537 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteT2FrameIndex()
555 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteT2FrameIndex()
DARMBaseInstrInfo.cpp1641 MachineOperand &ImmOp = MI.getOperand(ImmIdx); in rewriteARMFrameIndex() local
1656 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteARMFrameIndex()
1669 ImmOp.ChangeToImmediate(ImmedOffset); in rewriteARMFrameIndex()
/external/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp282 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue()); in foldOperand() local
283 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII); in foldOperand()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86MCInstLower.cpp232 unsigned ImmOp = Inst.getNumOperands() - 1; in SimplifyShortImmForm() local
233 assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() && in SimplifyShortImmForm()
244 MCOperand Saved = Inst.getOperand(ImmOp); in SimplifyShortImmForm()
/external/llvm/lib/Target/X86/AsmParser/
DX86Operand.h48 struct ImmOp { struct
65 struct ImmOp Imm;
DX86AsmParser.cpp2238 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, in ParseInstruction() local
2240 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); in ParseInstruction()
2265 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, in ParseInstruction() local
2267 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); in ParseInstruction()
2292 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, in ParseInstruction() local
2294 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); in ParseInstruction()
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1153 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1157 dag InOperandList = (ins ROWS:$ws, ImmOp:$m);
1181 SplatComplexPattern ImmOp, RegisterOperand ROWD,
1184 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1187 SplatComplexPattern ImmOp, RegisterOperand ROWD,
1190 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1204 ValueType VecTy, Operand ImmOp, ImmLeaf Imm,
1208 dag InOperandList = (ins ROWS:$ws, ImmOp:$n);
1216 Operand ImmOp, ImmLeaf Imm,
1219 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n);
[all …]
DMipsDSPInstrInfo.td327 Operand ImmOp, ImmLeaf immPat, InstrItinClass itin,
330 dag InOperandList = (ins ImmOp:$imm);
382 Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
384 dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
DMips64InstrInfo.td387 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :
388 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp253 unsigned ImmOp = Inst.getNumOperands() - 1; in SimplifyShortImmForm() local
255 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && in SimplifyShortImmForm()
266 MCOperand Saved = Inst.getOperand(ImmOp); in SimplifyShortImmForm()
/external/llvm/lib/Target/Lanai/AsmParser/
DLanaiAsmParser.cpp109 struct ImmOp { struct
123 struct ImmOp Imm;
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp206 struct ImmOp { struct in __anoncba7d3b40111::SparcOperand
219 struct ImmOp Imm;
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp611 struct ImmOp { struct in __anond0efcad40311::MipsOperand
627 struct ImmOp Imm;
2313 const MCOperand &ImmOp = Inst.getOperand(1); in expandLoadImm() local
2314 assert(ImmOp.isImm() && "expected immediate operand kind"); in expandLoadImm()
2318 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, in expandLoadImm()
2591 const MCOperand &ImmOp = Inst.getOperand(1); in expandBranchImm() local
2592 assert(ImmOp.isImm() && "expected immediate operand kind"); in expandBranchImm()
2611 int64_t ImmValue = ImmOp.getImm(); in expandBranchImm()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp193 struct ImmOp { struct in __anon26fd99540211::AArch64Operand
255 struct ImmOp Imm;
4001 AArch64Operand &ImmOp = static_cast<AArch64Operand &>(*Operands[2]); in MatchAndEmitInstruction() local
4002 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) { in MatchAndEmitInstruction()
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp335 struct ImmOp { struct
350 struct ImmOp Imm;
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp138 struct ImmOp { struct in __anon2fa8e53e0111::AMDGPUOperand
155 ImmOp Imm;
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp504 struct ImmOp { struct in __anonef5d38c20311::ARMOperand
575 struct ImmOp Imm;
4775 int CondOp = -1, ImmOp = -1; in cvtThumbBranches() local
4778 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; in cvtThumbBranches()
4781 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; in cvtThumbBranches()
4814 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
4821 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
4827 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); in cvtThumbBranches()

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