Home
last modified time | relevance | path

Searched refs:MI (Results 1 – 25 of 1058) sorted by relevance

12345678910>>...43

/external/llvm/lib/Target/X86/InstPrinter/
DX86ATTInstPrinter.h28 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
33 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
38 void printInstruction(const MCInst *MI, raw_ostream &OS);
41 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
44 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
45 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
46 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
[all …]
DX86IntelInstPrinter.h29 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
33 void printInstruction(const MCInst *MI, raw_ostream &O);
36 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
38 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O);
40 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
[all …]
DX86InstComments.cpp174 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT, in getRegOperandVectorVT() argument
176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
182 static MVT getZeroExtensionResultType(const MCInst *MI) { in getZeroExtensionResultType() argument
183 switch (MI->getOpcode()) { in getZeroExtensionResultType()
189 return getRegOperandVectorVT(MI, MVT::i16, 0); in getZeroExtensionResultType()
195 return getRegOperandVectorVT(MI, MVT::i32, 0); in getZeroExtensionResultType()
203 return getRegOperandVectorVT(MI, MVT::i64, 0); in getZeroExtensionResultType()
208 static std::string getMaskName(const MCInst *MI, const char *DestName, in getMaskName() argument
215 switch (MI->getOpcode()) { in getMaskName()
281 MaskRegName = getRegName(MI->getOperand(1).getReg()); in getMaskName()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h46 unsigned isLoadFromStackSlot(const MachineInstr &MI,
54 unsigned isStoreToStackSlot(const MachineInstr &MI,
189 bool expandPostRAPseudo(MachineInstr &MI) const override;
203 MachineBasicBlock::iterator MI) const override;
206 bool isPredicated(const MachineInstr &MI) const override;
210 bool PredicateInstruction(MachineInstr &MI,
221 bool DefinesPredicate(MachineInstr &MI,
227 bool isPredicable(MachineInstr &MI) const override;
231 bool isSchedulingBoundary(const MachineInstr &MI,
250 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
85 void emitInstruction(const MachineInstr &MI);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
104 unsigned getAddrModeSBit(const MachineInstr &MI,
[all …]
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp51 bool LowerSubregToReg(MachineInstr *MI);
52 bool LowerCopy(MachineInstr *MI);
54 void TransferImplicitDefs(MachineInstr *MI);
68 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument
69 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs()
72 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs()
73 MachineOperand &MO = MI->getOperand(i); in TransferImplicitDefs()
80 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument
81 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg()
82 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp44 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
45 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
46 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
47 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
48 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
49 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
67 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
68 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
69 !MI.getOperand(0).isTied()) in tieOpsIfNeeded()
70 MI.tieOperands(0, 1); in tieOpsIfNeeded()
[all …]
DSystemZAsmPrinter.cpp31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { in lowerRILow() argument
32 if (MI->isCompare()) in lowerRILow()
34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) { in lowerRIHigh() argument
46 if (MI->isCompare()) in lowerRIHigh()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DExpandPostRAPseudos.cpp54 bool LowerSubregToReg(MachineInstr *MI);
55 bool LowerCopy(MachineInstr *MI);
57 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
59 void TransferImplicitDefs(MachineInstr *MI);
73 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg, in TransferDeadFlag() argument
76 prior(MachineBasicBlock::iterator(MI)); ; --MII) { in TransferDeadFlag()
79 assert(MII != MI->getParent()->begin() && in TransferDeadFlag()
88 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument
89 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs()
92 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs()
[all …]
DTargetInstrInfoImpl.cpp60 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, in commuteInstruction() argument
62 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction()
64 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstruction()
68 if (!findCommutedOpIndices(MI, Idx1, Idx2)) { in commuteInstruction()
71 Msg << "Don't know how to commute: " << *MI; in commuteInstruction()
75 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstruction()
77 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstruction()
78 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction()
79 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction()
80 bool Reg1IsKill = MI->getOperand(Idx1).isKill(); in commuteInstruction()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.h28 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
35 void printInstruction(const MCInst *MI, raw_ostream &O);
39 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
47 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
48 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
[all …]
DARMInstPrinter.cpp53 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
55 unsigned Opcode = MI->getOpcode(); in printInst()
60 const MCOperand &Dst = MI->getOperand(0); in printInst()
61 const MCOperand &MO1 = MI->getOperand(1); in printInst()
62 const MCOperand &MO2 = MI->getOperand(2); in printInst()
63 const MCOperand &MO3 = MI->getOperand(3); in printInst()
66 printSBitModifierOperand(MI, 6, O); in printInst()
67 printPredicateOperand(MI, 4, O); in printInst()
80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
[all …]
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() argument
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
34 return MI.getOperand(OpNo).getReg() == R; in isReg()
79 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
81 switch (MI->getOpcode()) { in printInst()
91 printSaveRestore(MI, O); in printInst()
96 printSaveRestore(MI, O); in printInst()
101 printSaveRestore(MI, O); in printInst()
106 printSaveRestore(MI, O); in printInst()
112 if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) in printInst()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp34 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
37 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
38 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
39 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
40 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
50 printOperand(MI, 0, O); in printInst()
52 printOperand(MI, 1, O); in printInst()
60 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
61 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
63 printOperand(MI, 0, O); in printInst()
[all …]
/external/llvm/lib/Target/AMDGPU/InstPrinter/
DAMDGPUInstPrinter.h27 void printInstruction(const MCInst *MI, raw_ostream &O);
30 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
36 void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
38 void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
40 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printNamedBit(const MCInst* MI, unsigned OpNo, raw_ostream& O,
[all …]
DAMDGPUInstPrinter.cpp26 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument
29 printInstruction(MI, OS); in printInst()
34 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, in printU4ImmOperand() argument
36 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
39 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, in printU8ImmOperand() argument
41 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
44 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, in printU16ImmOperand() argument
46 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmOperand()
49 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, in printU32ImmOperand() argument
51 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.h26 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
31 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
33 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
35 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
41 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
44 void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
46 void printSORegImmOperand(const MCInst *MI, unsigned OpNum,
49 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
51 void printAddrModeTBH(const MCInst *MI, unsigned OpNum,
53 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum,
[all …]
DARMInstPrinter.cpp71 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
73 unsigned Opcode = MI->getOpcode(); in printInst()
80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
82 const MCOperand &MO2 = MI->getOperand(2); in printInst()
83 const MCOperand &MO3 = MI->getOperand(3); in printInst()
86 printSBitModifierOperand(MI, 6, STI, O); in printInst()
87 printPredicateOperand(MI, 4, STI, O); in printInst()
103 const MCOperand &Dst = MI->getOperand(0); in printInst()
104 const MCOperand &MO1 = MI->getOperand(1); in printInst()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/
DX86InstComments.cpp29 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, in EmitAnyX86InstComments() argument
35 switch (MI->getOpcode()) { in EmitAnyX86InstComments()
37 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
38 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
43 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
44 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
50 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
55 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
[all …]
/external/llvm/lib/Target/Lanai/InstPrinter/
DLanaiInstPrinter.cpp36 bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument
40 printOperand(MI, OpNo0, OS); in printInst()
42 printOperand(MI, OpNo1, OS); in printInst()
46 static bool usesGivenOffset(const MCInst *MI, int AddOffset) { in usesGivenOffset() argument
47 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
49 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
50 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
53 static bool isPreIncrementForm(const MCInst *MI, int AddOffset) { in isPreIncrementForm() argument
54 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
55 return LPAC::isPreOp(AluCode) && usesGivenOffset(MI, AddOffset); in isPreIncrementForm()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUAsmPrinter.cpp51 void printInstruction(const MachineInstr *MI, raw_ostream &OS);
55 void EmitInstruction(const MachineInstr *MI) { in EmitInstruction() argument
58 printInstruction(MI, OS); in EmitInstruction()
63 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { in printOperand() argument
64 const MachineOperand &MO = MI->getOperand(OpNo); in printOperand()
74 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
77 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
83 printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) in printU7ImmOperand() argument
85 unsigned int value = MI->getOperand(OpNo).getImm(); in printU7ImmOperand()
91 printShufAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) in printShufAddr() argument
[all …]
/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp56 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
59 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
60 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
61 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
62 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
72 printOperand(MI, 0, O); in printInst()
74 printOperand(MI, 1, O); in printInst()
82 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
83 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
85 printOperand(MI, 0, O); in printInst()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp67 unsigned getBinaryCodeForInstr(const MCInst &MI,
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/SystemZ/InstPrinter/
DSystemZInstPrinter.cpp52 void SystemZInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
55 printInstruction(MI, O); in printInst()
64 static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { in printUImmOperand() argument
65 int64_t Value = MI->getOperand(OpNum).getImm(); in printUImmOperand()
71 static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { in printSImmOperand() argument
72 int64_t Value = MI->getOperand(OpNum).getImm(); in printSImmOperand()
77 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum, in printU1ImmOperand() argument
79 printUImmOperand<1>(MI, OpNum, O); in printU1ImmOperand()
82 void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum, in printU2ImmOperand() argument
84 printUImmOperand<2>(MI, OpNum, O); in printU2ImmOperand()
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h44 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
50 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
86 unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
89 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
106 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
120 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
124 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
129 MachineBasicBlock::iterator MI, unsigned SrcReg,
135 MachineBasicBlock::iterator MI, unsigned DestReg,
139 bool expandPostRAPseudo(MachineInstr &MI) const override;
[all …]

12345678910>>...43