| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 386 const MachineInstr &MI1, in produceSameValue() argument
388 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
570 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
573 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
578 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
585 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
591 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
593 std::swap(MI1, MI2); in hasReassociableSibling()
599 return MI1->getOpcode() == AssocOpcode && in hasReassociableSibling()
600 hasReassociableOperands(*MI1, MBB) && in hasReassociableSibling()
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| D | MachineInstr.cpp | 905 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) { in hasIdenticalMMOs() argument
906 auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end(); in hasIdenticalMMOs()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 844 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements() argument
848 if (getPredicateSense(MI1, HII) == PK_Unknown || in arePredicatesComplements()
853 SUnit *SU = MIToSUnit[&MI1]; in arePredicatesComplements()
901 unsigned PReg1 = getPredicatedRegister(MI1, HII); in arePredicatesComplements()
906 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
907 HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2); in arePredicatesComplements()
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| D | HexagonVLIWPacketizer.h | 97 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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| D | HexagonInstrInfo.cpp | 2932 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr *MI1, in addLatencyToSchedule() argument
2934 if (isV60VectorInstruction(MI1) && isV60VectorInstruction(MI2)) in addLatencyToSchedule()
2935 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 251 MachineInstr &MI1 = *MII; in ExpandFPMLxInstruction()
252 dbgs() << " " << MI1; in ExpandFPMLxInstruction()
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| D | ARMBaseInstrInfo.cpp | 1164 const MachineInstr *MI1, in produceSameValue() argument
1176 if (MI1->getOpcode() != Opcode) in produceSameValue()
1178 if (MI0->getNumOperands() != MI1->getNumOperands()) in produceSameValue()
1182 const MachineOperand &MO1 = MI1->getOperand(1); in produceSameValue()
1213 if (MI1->getOpcode() != Opcode) in produceSameValue()
1215 if (MI0->getNumOperands() != MI1->getNumOperands()) in produceSameValue()
1219 unsigned Addr1 = MI1->getOperand(1).getReg(); in produceSameValue()
1238 const MachineOperand &MO1 = MI1->getOperand(i); in produceSameValue()
1245 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
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| D | ARMBaseInstrInfo.h | 143 const MachineInstr *MI1,
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| /external/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 249 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
364 int64_t OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, unsigned N1, in getAddrDispShift() argument
367 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp); in getAddrDispShift()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetInstrInfo.h | 242 const MachineInstr *MI1,
759 const MachineInstr *MI1,
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 319 MachineInstr &MI1 = *MII; in ExpandFPMLxInstruction()
320 dbgs() << " " << MI1; in ExpandFPMLxInstruction()
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| D | ARMBaseInstrInfo.cpp | 1451 const MachineInstr &MI1, in produceSameValue() argument
1464 if (MI1.getOpcode() != Opcode) in produceSameValue()
1466 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1470 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue()
1502 if (MI1.getOpcode() != Opcode) in produceSameValue()
1504 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1508 unsigned Addr1 = MI1.getOperand(1).getReg(); in produceSameValue()
1527 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue()
1534 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
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| D | ARMBaseInstrInfo.h | 205 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TargetInstrInfoImpl.cpp | 214 const MachineInstr *MI1, in produceSameValue() argument
216 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 440 const MachineInstr &MI1,
|