| /external/vixl/test/aarch32/ |
| D | test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc | 174 {NZCVFlag, 0xffffffff, 0xffffffff},
200 {NZCVFlag, 0xffff8001, 0xffff8001},
225 {NZCVFlag, 0xfffffffd, 0xfffffffd},
241 {NZCVFlag, 0xffffff81, 0xffffff81},
256 {NZCVFlag, 0xfffffffe, 0xfffffffe},
261 {NZCVFlag, 0x00007ffd, 0x00007ffd},
269 {NZCVFlag, 0x7ffffffd, 0x7ffffffd},
276 {NZCVFlag, 0xffff8003, 0xffff8003},
312 {NZCVFlag, 0x00000000, 0x00000000},
324 {NZCVFlag, 0x0000007d, 0x0000007d},
[all …]
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 210 {NZCVFlag, 0xabababab, 0xabababab, 0xabababab}};
226 {NZCVFlag, 0x00007ffe, 0x00007ffe, 0xfffffffe},
229 {NZCVFlag, 0x00000002, 0x00000002, 0xfffffffd},
231 {NZCVFlag, 0xfffffffd, 0xfffffffd, 0x00007ffe},
235 {NZCVFlag, 0x00007fff, 0x00007fff, 0x00007ffd},
236 {NZCVFlag, 0x55555555, 0x55555555, 0xffffff82},
272 {NZCVFlag, 0x0000007e, 0x0000007e, 0x33333333},
290 {NZCVFlag, 0x7ffffffd, 0x7ffffffd, 0x0000007e},
298 {NZCVFlag, 0x00000002, 0x00000002, 0x33333333},
320 {NZCVFlag, 0x00007ffd, 0x00007ffd, 0x00000000},
[all …]
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| D | test-utils-aarch32.h | 63 const uint32_t NZCVFlag = NFlag | ZFlag | CFlag | VFlag; variable
145 return dump_.flags_ & NZCVFlag; in flags_nzcv()
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| D | test-utils-aarch32.cc | 188 VIXL_ASSERT((expected & ~NZCVFlag) == 0); in EqualNzcv()
189 VIXL_ASSERT((result & ~NZCVFlag) == 0); in EqualNzcv()
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| D | test-simulator-cond-rd-operand-imm16-t32.cc | 174 {NZCVFlag, 0xabababab}};
508 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-const-a32.cc | 180 {NZCVFlag, 0xabababab}};
555 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-const-t32.cc | 180 {NZCVFlag, 0xabababab}};
670 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-a32.cc | 187 {NZCVFlag, 0xabababab, 0xabababab}};
687 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 181 {NZCVFlag, 0xabababab, 0xabababab}};
766 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-t32.cc | 187 {NZCVFlag, 0xabababab, 0xabababab}};
687 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 181 {NZCVFlag, 0xabababab, 0xabababab}};
766 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 178 {NZCVFlag, 0xabababab, 0xabababab, 0xabababab}};
957 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-a32-q.cc | 471 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper()
494 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-a32-sel.cc | 464 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper()
487 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32-q.cc | 471 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper()
494 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32-sel.cc | 464 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper()
487 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-t32-ge.cc | 487 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper()
510 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-rn-rm-a32-ge.cc | 487 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper()
510 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 210 {NZCVFlag, 0xabababab, 0xabababab, 0xabababab}};
1174 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 183 {NZCVFlag, 0xabababab, 0xabababab}};
1070 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 183 {NZCVFlag, 0xabababab, 0xabababab}};
1060 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 183 {NZCVFlag, 0xabababab, 0xabababab}};
1060 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 183 {NZCVFlag, 0xabababab, 0xabababab}};
1070 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 184 {NZCVFlag, 0xabababab, 0xabababab, 0xabababab}};
1175 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper()
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| /external/vixl/test/aarch64/ |
| D | test-utils-aarch64.cc | 227 VIXL_ASSERT((expected & ~NZCVFlag) == 0); in EqualNzcv()
228 VIXL_ASSERT((result & ~NZCVFlag) == 0); in EqualNzcv()
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