Home
last modified time | relevance | path

Searched refs:b01 (Results 1 – 25 of 53) sorted by relevance

123

/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
39 def : AT<"S1E2W", 0b01, 0b100, 0b0111, 0b1000, 0b001>;
40 def : AT<"S1E3W", 0b01, 0b110, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
43 def : AT<"S12E1R", 0b01, 0b100, 0b0111, 0b1000, 0b100>;
44 def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>;
[all …]
DAArch64InstrInfo.td704 defm LSRV : Shift<0b01, "lsr", srl>;
802 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
807 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
888 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
909 defm ORN : LogicalReg<0b01, 1, "orn",
911 defm ORR : LogicalReg<0b01, 0, "orr", or>;
1004 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
1115 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1117 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1276 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
[all …]
DAArch64InstrFormats.td1020 let Inst{20-19} = 0b01;
1035 let Inst{20-19} = 0b01;
2402 let Inst{25-24} = 0b01;
3163 let Inst{11-10} = 0b01;
3595 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3601 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3646 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3655 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3717 let Inst{23-22} = 0b01; // 64-bit FPR flag
3733 let Inst{23-22} = 0b01; // 64-bit FPR flag
[all …]
/external/skia/src/core/
DSkMatrix44.cpp455 double b01 = a00 * a12 - a02 * a10; in determinant() local
468 return b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in determinant()
570 double b01 = a00 * a12 - a02 * a10; in invert() local
580 double det = b00 * b11 - b01 * b10 + b03 * b08; in invert()
591 b01 *= invdet; in invert()
606 inverse->fMat[1][2] = SkDoubleToMScalar(-b01); in invert()
614 inverse->fMat[3][2] = SkDoubleToMScalar(a31 * b01 - a30 * b03 - a32 * b00); in invert()
628 double b01 = a00 * a12 - a02 * a10; in invert() local
641 double det = b00 * b11 - b01 * b10 + b02 * b09 + b03 * b08 - b04 * b07 + b05 * b06; in invert()
652 b01 *= invdet; in invert()
[all …]
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td398 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
403 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
408 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
413 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
418 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
423 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
432 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
437 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
442 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
447 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td101 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),
148 let Inst{24-23} = 0b01; // Increment After
157 let Inst{24-23} = 0b01; // Increment After
176 let Inst{24-23} = 0b01; // Increment After
189 let Inst{24-23} = 0b01; // Increment After
302 let Inst{24-23} = 0b01; // Increment After
309 let Inst{24-23} = 0b01; // Increment After
465 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
[all …]
DARMInstrNEON.td3239 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3253 def v4f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3266 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3280 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3299 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3307 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3323 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3340 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3355 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3374 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
[all …]
DARMInstrThumb2.td599 let Inst{26-25} = 0b01;
612 let Inst{26-25} = 0b01;
683 let Inst{26-25} = 0b01;
696 let Inst{26-25} = 0b01;
803 let Inst{26-25} = 0b01;
817 let Inst{26-25} = 0b01;
846 let Inst{26-25} = 0b01;
859 let Inst{26-25} = 0b01;
942 let Inst{26-25} = 0b01;
957 let Inst{26-25} = 0b01;
[all …]
/external/clang/test/CodeGenCXX/
Dbitfield.cpp14 unsigned b01 : 2; member
52 return s->b01; in read01()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td71 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
75 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
108 let Inst{24-23} = 0b01; // Increment After
117 let Inst{24-23} = 0b01; // Increment After
136 let Inst{24-23} = 0b01; // Increment After
149 let Inst{24-23} = 0b01; // Increment After
289 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
294 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
344 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
352 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
[all …]
DARMInstrNEON.td2512 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2532 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2558 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2566 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2582 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2599 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2614 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2633 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2644 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2653 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
[all …]
DARMInstrThumb2.td511 let Inst{26-25} = 0b01;
523 let Inst{26-25} = 0b01;
589 let Inst{26-25} = 0b01;
601 let Inst{26-25} = 0b01;
677 let Inst{26-25} = 0b01;
690 let Inst{26-25} = 0b01;
719 let Inst{26-25} = 0b01;
732 let Inst{26-25} = 0b01;
840 let Inst{26-25} = 0b01;
854 let Inst{26-25} = 0b01;
[all …]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-CPS2p-arm.txt3 # invalid imod value (0b01)
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td93 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
500 let Inst{25-24} = !if(isHi, 0b10, 0b01);
1088 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1094 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1101 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1107 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1156 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1358 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1569 let Inst{24-23} = !if (isPred, 0b10, 0b01);
2202 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
[all …]
DHexagonInstrInfoV4.td238 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
241 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
315 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
409 let Inst{13-12} = 0b01;
751 def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
848 def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
906 let Inst{27-26} = 0b01;
965 let Inst{27-26} = 0b01;
1025 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1158 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
[all …]
DHexagonInstrInfoVector.td166 def S2_lsr_r_vw : T_S3op_shiftVect < "vlsrw", 0b00, 0b01>;
171 def S2_asr_r_vh : T_S3op_shiftVect < "vasrh", 0b01, 0b00>;
172 def S2_lsr_r_vh : T_S3op_shiftVect < "vlsrh", 0b01, 0b01>;
173 def S2_asl_r_vh : T_S3op_shiftVect < "vaslh", 0b01, 0b10>;
174 def S2_lsl_r_vh : T_S3op_shiftVect < "vlslh", 0b01, 0b11>;
DHexagonInstrEnc.td451 let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} };
468 let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} };
638 let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} };
655 let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} };
780 class V6_vshuff_enc : Enc_COPROC_VX_cards<0b01>;
976 class Y6_l2gcleanpa_enc : Enc_ST_l2gclean_pa<0b01>;
DHexagonSystemInst.td133 def J2_pause : J2_MISC_TRAP_PAUSE<"pause", 0b01>;
/external/eigen/Eigen/src/SparseLU/
DSparseLU_gemm_kernel.h74 Packet b00, b10, b20, b30, b01, b11, b21, b31; in sparselu_gemm() local
79 { b01 = pset1<Packet>(Bc1[0]); } in sparselu_gemm()
112 KMADD(c1, a0, b01, t1) \ in sparselu_gemm()
/external/libvpx/libvpx/vpx_dsp/arm/
Davg_neon.c214 const uint8x16_t b01 = vcombine_u8(vld1_u8(b), vld1_u8(b + b_stride)); in vpx_minmax_8x8_neon() local
223 const uint8x16_t ab01_diff = vabdq_u8(a01, b01); in vpx_minmax_8x8_neon()
/external/libvpx/libvpx/vp8/common/arm/neon/
Dbilinearpredict_neon.c50 uint8x16_t b01, b23; in vp8_bilinear_predict4x4_neon() local
69 b01 = vreinterpretq_u8_u64(vshrq_n_u64(vreinterpretq_u64_u8(a01), 8)); in vp8_bilinear_predict4x4_neon()
77 c2 = vzip_u32(vreinterpret_u32_u8(vget_low_u8(b01)), in vp8_bilinear_predict4x4_neon()
78 vreinterpret_u32_u8(vget_high_u8(b01))); in vp8_bilinear_predict4x4_neon()
/external/sl4a/Common/src/com/googlecode/android_scripting/facade/bluetooth/
DBluetoothHidFacade.java188 byte[] bts = {0b01,0b10,0b11,0b100}; in testByte()
/external/valgrind/none/tests/ppc64/
Dtest_isa_2_06_part1.stdout.exp-LE90 fcfids 0020000000000b01 => (raw sp) 5a000000)
93 fcfids 8020000000000b01 => (raw sp) deffc000)
104 fcfidus 0020000000000b01 => (raw sp) 5a000000)
107 fcfidus 8020000000000b01 => (raw sp) 5f002000)
118 fcfidu 0020000000000b01 => (raw sp) 4340000000000580)
121 fcfidu 8020000000000b01 => (raw sp) 43e0040000000001)
/external/llvm/lib/Target/AVR/
DAVRInstrFormats.td183 // a = regular/postinc/predec (reg = 0b00, postinc = 0b01, predec = 0b10)
234 let Inst{3-2} = 0b01;
278 // ff = 0b01 for FMUL
/external/llvm/test/TableGen/
Dif.td38 !if(!eq(s, 16), 0b01,

123