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Searched refs:getNode (Results 1 – 25 of 376) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp442 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
447 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
461 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
470 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
476 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
483 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
487 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
526 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) in isOneUseSetCC()
541 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); in ReassociateOps()
545 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, in ReassociateOps()
[all …]
DLegalizeIntegerTypes.cpp142 if (Res.getNode()) in PromoteIntegerResult()
155 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), in PromoteIntRes_AssertSext()
162 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), in PromoteIntRes_AssertZext()
222 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
226 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
233 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
247 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
251 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
256 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
[all …]
DLegalizeVectorOps.cpp106 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) in TranslateLegalizeResults()
117 SDNode* Node = Op.getNode(); in LegalizeOp()
125 SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0); in LegalizeOp()
210 if (Tmp1.getNode()) { in LegalizeOp()
226 Result = DAG.UnrollVectorOp(Op.getNode()); in LegalizeOp()
247 assert(Op.getNode()->getNumValues() == 1 && in PromoteVectorOp()
255 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); in PromoteVectorOp()
260 Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size()); in PromoteVectorOp()
262 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in PromoteVectorOp()
280 return DAG.UnrollVectorOp(Op.getNode()); in ExpandVSELECT()
[all …]
DLegalizeDAG.cpp277 Node = Node->getOperand(0).getNode(); in FindCallStartFromCallEnd()
320 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, in LegalizeAllNodesNotLeadingTo()
399 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); in ExpandUnalignedStore()
438 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, in ExpandUnalignedStore()
440 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); in ExpandUnalignedStore()
461 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], in ExpandUnalignedStore()
476 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, in ExpandUnalignedStore()
491 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); in ExpandUnalignedStore()
511 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in ExpandUnalignedLoad()
[all …]
DSelectionDAGBuilder.cpp130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); in getCopyFromParts()
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, in getCopyFromParts()
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); in getCopyFromParts()
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); in getCopyFromParts()
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); in getCopyFromParts()
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); in getCopyFromParts()
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
[all …]
DLegalizeTypesGeneric.cpp57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
64 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
65 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
71 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
72 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
85 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, in ExpandRes_BITCAST()
87 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, in ExpandRes_BITCAST()
[all …]
DLegalizeVectorTypes.cpp121 if (R.getNode()) in ScalarizeVectorResult()
128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), in ScalarizeVecRes_BinOp()
140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), in ScalarizeVecRes_BITCAST()
156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), in ScalarizeVecRes_FP_ROUND()
170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), in ScalarizeVecRes_FPOWI()
181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); in ScalarizeVecRes_INSERT_VECTOR_ELT()
209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); in ScalarizeVecRes_UnaryOp()
216 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT, in ScalarizeVecRes_InregOp()
226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); in ScalarizeVecRes_SCALAR_TO_VECTOR()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelDAGToDAG.cpp86 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0; in hasBaseOrIndexReg()
94 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) in isRIPRelative()
107 if (Base_Reg.getNode() != 0) in dump()
108 Base_Reg.getNode()->dump(); in dump()
114 if (IndexReg.getNode() != 0) in dump()
115 IndexReg.getNode()->dump(); in dump()
257 if (AM.Segment.getNode()) in getAddressOperands()
365 if (Chain.getNode() == Load.getNode()) in MoveBelowOrigChain()
371 if (Chain.getOperand(i).getNode() == Load.getNode()) in MoveBelowOrigChain()
376 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(), in MoveBelowOrigChain()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp578 AddToWorklist(Op.getNode()); in deleteAndRecombine()
660 const SDNodeFlags *Flags = Op.getNode()->getFlags(); in GetNegatedExpression()
676 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
681 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
695 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
705 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
711 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
718 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
722 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
744 !TLI.isConstTrueVal(N.getOperand(2).getNode()) || in isSetCCEquivalent()
[all …]
DLegalizeVectorOps.cpp181 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) in TranslateLegalizeResults()
192 SDNode* Node = Op.getNode(); in LegalizeOp()
199 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0); in LegalizeOp()
203 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); in LegalizeOp()
231 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); in LegalizeOp()
403 assert(Op.getNode()->getNumValues() == 1 && in Promote()
416 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); in Promote()
418 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); in Promote()
423 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags()); in Promote()
427 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl)); in Promote()
[all …]
DLegalizeDAG.cpp191 UpdatedNodes->insert(New.getNode()); in ReplaceNode()
192 ReplacedNode(Old.getNode()); in ReplaceNode()
203 UpdatedNodes->insert(New[i].getNode()); in ReplaceNode()
333 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); in PerformInsertVectorEltInMemory()
345 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3, in PerformInsertVectorEltInMemory()
347 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); in PerformInsertVectorEltInMemory()
367 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
430 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, in OptimizeFloatStore()
437 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); in OptimizeFloatStore()
456 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { in LegalizeStoreOps()
[all …]
DLegalizeIntegerTypes.cpp162 if (Res.getNode()) in PromoteIntegerResult()
175 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
182 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
263 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
267 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
271 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); in PromoteIntRes_BITCAST()
280 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
294 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
298 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
305 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
[all …]
DLegalizeTypesGeneric.cpp63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
75 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
76 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
89 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
90 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
100 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
101 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
[all …]
DTargetLowering.cpp264 SDValue Tmp = DAG.getNode( in softenSetCCOperands()
270 NewLHS = DAG.getNode( in softenSetCCOperands()
274 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); in softenSetCCOperands()
360 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), in ShrinkDemandedConstant()
383 assert(Op.getNode()->getNumValues() == 1 && in ShrinkDemandedOp()
392 if (!Op.getNode()->hasOneUse()) in ShrinkDemandedOp()
407 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
408 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
409 Op.getNode()->getOperand(0)), in ShrinkDemandedOp()
410 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
[all …]
DResourcePriorityQueue.cpp78 const SDNode *ScegN = PredSU->getNode(); in numberRCValPredInSU()
116 const SDNode *ScegN = SuccSU->getNode(); in numberRCValSuccInSU()
134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
247 if (!SU || !SU->getNode()) in isResourceAvailable()
252 if (SU->getNode()->getGluedNode()) in isResourceAvailable()
257 if (SU->getNode()->isMachineOpcode()) in isResourceAvailable()
258 switch (SU->getNode()->getMachineOpcode()) { in isResourceAvailable()
261 SU->getNode()->getMachineOpcode()))) in isResourceAvailable()
292 if (!isResourceAvailable(SU) || SU->getNode()->getGluedNode()) { in reserveResources()
297 if (SU->getNode() && SU->getNode()->isMachineOpcode()) { in reserveResources()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp59 if (Base.Reg.getNode() != 0) in dump()
60 Base.Reg.getNode()->dump(); in dump()
69 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump(); in dump()
210 AM.Base.Reg.getNode() == 0) { in MatchAddress()
227 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) { in MatchAddress()
232 if (AM.IndexReg.getNode() || AM.isRI) { in MatchAddress()
240 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) { in MatchAddress()
246 SDValue RHS = N.getNode()->getOperand(1); in MatchAddress()
248 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); in MatchAddress()
252 if (Zero.getNode()->getNodeId() == -1 || in MatchAddress()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
84 Op.getNode()->dump(); in LowerOperation()
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
[all …]
DAMDILISelLowering.cpp329 DST = SDValue(Op.getNode(), 0); in LowerSDIV()
348 DST = SDValue(Op.getNode(), 0); in LowerSREM()
362 Nodes1 = DAG.getNode(AMDGPUISD::VBUILD, in LowerBUILD_VECTOR()
384 Nodes1 = DAG.getNode( in LowerBUILD_VECTOR()
395 Nodes1 = DAG.getNode( in LowerBUILD_VECTOR()
406 Nodes1 = DAG.getNode( in LowerBUILD_VECTOR()
434 Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data); in LowerSIGN_EXTEND_INREG()
440 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
480 Result = DAG.getNode( in LowerBRCOND()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp84 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext()); in ExpandLibCall()
598 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, in LowerLOAD()
618 rotate = DAG.getNode(ISD::ADD, dl, PtrVT, in LowerLOAD()
637 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); in LowerLOAD()
643 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); in LowerLOAD()
646 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, in LowerLOAD()
653 rotate = DAG.getNode(ISD::ADD, dl, PtrVT, in LowerLOAD()
670 result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::i128, in LowerLOAD()
677 result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, in LowerLOAD()
678 DAG.getNode(ISD::BITCAST, dl, vecVT, result)); in LowerLOAD()
[all …]
DSPUISelDAGToDAG.cpp124 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in getCarryGenerateShufMask()
139 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in getBorrowGenerateShufMask()
186 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) || in emitBuildVector()
188 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) || in emitBuildVector()
189 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) || in emitBuildVector()
190 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) || in emitBuildVector()
191 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) || in emitBuildVector()
193 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) || in emitBuildVector()
194 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) || in emitBuildVector()
195 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) { in emitBuildVector()
[all …]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp656 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain); in LowerReturn()
791 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
797 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
815 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
821 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
856 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(G), ConstPtrVT, GA); in LowerGlobalAddress()
926 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT, in LowerINTRINSIC_WO_CHAIN()
930 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
934 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT, in LowerINTRINSIC_WO_CHAIN()
940 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT, in LowerINTRINSIC_WO_CHAIN()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp183 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); in LowerOperation()
217 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), in LowerSELECT_CC()
219 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), in LowerSELECT_CC()
230 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
240 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
242 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
254 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, in BuildGetId()
292 SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl), in LowerGlobalTLSAddress()
294 return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset); in LowerGlobalTLSAddress()
305 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); in LowerBlockAddress()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp1132 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1135 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1136 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1147 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1148 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1162 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1181 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); in LowerMemOpCallTo()
1195 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
1203 if (StackPtr.getNode() == 0) in PassF64ArgInRegs()
1283 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) in isRIPRelative()
107 if (Base_Reg.getNode()) in dump()
108 Base_Reg.getNode()->dump(); in dump()
114 if (IndexReg.getNode()) in dump()
115 IndexReg.getNode()->dump(); in dump()
280 if (AM.Segment.getNode()) in getAddressOperands()
316 User->getOperand(1).getNode() == N) { in shouldAvoidImmediateInstFormsForSize()
341 if (OtherOp.getNode() == N) in shouldAvoidImmediateInstFormsForSize()
348 OtherOp->getOperand(1).getNode()))) in shouldAvoidImmediateInstFormsForSize()
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/external/llvm/unittests/IR/
DDominatorTreeTest.cpp180 EXPECT_EQ(DT->getNode(BB0)->getDFSNumIn(), 0UL); in runOnFunction()
181 EXPECT_EQ(DT->getNode(BB0)->getDFSNumOut(), 7UL); in runOnFunction()
182 EXPECT_EQ(DT->getNode(BB1)->getDFSNumIn(), 1UL); in runOnFunction()
183 EXPECT_EQ(DT->getNode(BB1)->getDFSNumOut(), 2UL); in runOnFunction()
184 EXPECT_EQ(DT->getNode(BB2)->getDFSNumIn(), 5UL); in runOnFunction()
185 EXPECT_EQ(DT->getNode(BB2)->getDFSNumOut(), 6UL); in runOnFunction()
186 EXPECT_EQ(DT->getNode(BB4)->getDFSNumIn(), 3UL); in runOnFunction()
187 EXPECT_EQ(DT->getNode(BB4)->getDFSNumOut(), 4UL); in runOnFunction()
195 EXPECT_EQ(DT->getNode(BB0)->getDFSNumIn(), 0UL); in runOnFunction()
196 EXPECT_EQ(DT->getNode(BB0)->getDFSNumOut(), 9UL); in runOnFunction()
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