| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineOperand.h | 191 bool isReg() const { return OpKind == MO_Register; } in isReg() function
222 assert(isReg() && "This is not a register operand!"); in getReg()
227 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
232 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
237 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
242 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
247 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
252 assert(isReg() && "Wrong MachineOperand accessor"); in isKill()
257 assert(isReg() && "Wrong MachineOperand accessor"); in isUndef()
262 assert(isReg() && "Wrong MachineOperand accessor"); in isEarlyClobber()
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| /external/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
128 if (Op.isReg()) { in printOperand()
232 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
234 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
237 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
240 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
243 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
246 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); in printAlias()
249 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 192 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
195 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
200 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
230 bool isReg() const { return OpKind == MO_Register; } in isReg() function
268 assert(isReg() && "This is not a register operand!"); in getReg()
273 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
278 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
283 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
288 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
293 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 115 if (MCOp.isReg()) in getMachineOpValue()
149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
153 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
157 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
196 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
228 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
230 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
267 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
295 if (MCOp.isReg() || MCOp.isImm()) in getCallTargetOpValue()
308 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineInstr.cpp | 53 assert(isReg() && "Can only add reg operand to use lists"); in AddRegOperandToRegInfo()
144 if (isReg() && getParent() && getParent()->getParent() && in ChangeToImmediate()
160 if (isReg()) { in ChangeToRegister()
572 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && in ~MachineInstr()
592 if (Operands[i].isReg()) in RemoveRegOperandsFromUseLists()
602 if (Operands[i].isReg()) in AddRegOperandsToUseLists()
614 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
632 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
649 if (Operands[i].isReg()) in addOperand()
660 if (Operands[i].isReg()) in addOperand()
[all …]
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| D | TargetInstrInfoImpl.cpp | 64 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstruction()
75 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstruction()
131 if (!MI->getOperand(SrcOpIdx1).isReg() || in findCommutedOpIndices()
132 !MI->getOperand(SrcOpIdx2).isReg()) in findCommutedOpIndices()
149 if (MO.isReg()) { in PredicateInstruction()
366 if (!MI->getNumOperands() || !MI->getOperand(0).isReg()) in isReallyTriviallyReMaterializableGeneric()
406 if (!MO.isReg()) continue; in isReallyTriviallyReMaterializableGeneric()
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| D | DeadMachineInstructionElim.cpp | 71 if (MO.isReg() && MO.isDef()) { in isDead()
136 if (!MO.isReg() || !MO.isDef()) in runOnMachineFunction()
165 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
182 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
220 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
239 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
257 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
272 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
288 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 62 assert(FoldOp->isReg()); in FoldCandidate()
103 assert(Old.isReg()); in updateOperand()
175 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() || in tryAddToFoldList()
176 !MI->getOperand(CommuteIdx1).isReg())) in tryAddToFoldList()
200 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in foldOperand()
323 if (!FoldingImm && !OpToFold.isReg()) in runOnMachineFunction()
333 if (OpToFold.isReg() && in runOnMachineFunction()
344 if (Dst.isReg() && in runOnMachineFunction()
372 assert(Fold.OpToFold && Fold.OpToFold->isReg()); in runOnMachineFunction()
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| D | SIShrinkInstructions.cpp | 71 if (!MO->isReg()) in isVGPR()
150 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)) in foldImmediates()
154 if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) { in foldImmediates()
283 Src0.isReg()) { in runOnMachineFunction()
288 if (Src0.isReg() && Src0.getReg() == Dest.getReg()) { in runOnMachineFunction()
350 if (!Src2->isReg()) in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getDirectBrEncoding()
100 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getCondBrEncoding()
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getHA16Encoding()
122 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getLO16Encoding()
134 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
152 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
179 if (MO.isReg()) { in getMachineOpValue()
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 100 assert(isReg() && "Wrong MachineOperand accessor"); in setIsDef()
120 if (!isReg() || !isOnRegUseList()) in removeRegFromUses()
135 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToImmediate()
144 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToFPImmediate()
153 assert((!isReg() || !isTied()) && in ChangeToES()
165 assert((!isReg() || !isTied()) && in ChangeToMCSymbol()
187 bool WasReg = isReg(); in ChangeToRegister()
732 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
741 if (MO.isReg()) in AddRegOperandsToUseLists()
788 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
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| D | ImplicitNullChecks.cpp | 204 if (!MO.isReg() || !MO.getReg()) in rememberInstruction()
232 if (MO.isReg() && MO.getReg()) { in isSafeToHoist()
262 if (!MO.isReg() || !MO.getReg()) in isSafeToHoist()
339 if (!(MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 && in analyzeBlockForNullChecks()
434 assert(!(MO.isReg() && MO.isUse()) && in analyzeBlockForNullChecks()
436 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) in analyzeBlockForNullChecks()
542 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks()
552 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) in rewriteNullChecks()
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| D | LivePhysRegs.cpp | 48 if (O->isReg()) { in stepBackward()
61 if (!O->isReg() || !O->readsReg()) in stepBackward()
78 if (O->isReg()) { in stepForward()
99 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 118 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep()
286 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) in isCallDependent()
354 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg()) in cleanUpDotCur()
397 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
463 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand()
467 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
473 assert(Op1.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
479 assert(Op0.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
538 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
591 if (!MO.isReg()) in canPromoteToNewValueStore()
[all …]
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| D | HexagonExpandCondsets.cpp | 351 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) in updateKillFlags()
412 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
519 if (Op.isReg() && Op.isDef() && DefRegs.count(Op)) in updateDeadsInRange()
580 if (SO.isReg()) { in getCondTfrOpcode()
662 bool SameReg = (MS1.isReg() && DR == MS1.getReg()) || in split()
663 (MS2.isReg() && DR == MS2.getReg()); in split()
670 if ((MS1.isReg() && NewSR == MS1.getSubReg()) || in split()
671 (MS2.isReg() && NewSR == MS2.getSubReg())) in split()
695 if (Op.isReg()) in split()
726 if (!Op.isReg() || !Op.isDef()) in isPredicable()
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| D | HexagonHardwareLoops.cpp | 312 bool isReg() const { return Kind == CV_Register; } in isReg() function in __anonfb58bf460111::CountValue
316 assert(isReg() && "Wrong CountValue accessor"); in getReg()
320 assert(isReg() && "Wrong CountValue accessor"); in getSubReg()
329 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } in print()
644 if (Op1.isReg()) { in getLoopTripCount()
664 if (InitialValue->isReg()) { in getLoopTripCount()
671 if (EndValue->isReg()) { in getLoopTripCount()
698 if (Start->isReg()) { in computeCount()
704 if (End->isReg()) { in computeCount()
711 if (!Start->isReg() && !Start->isImm()) in computeCount()
[all …]
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| D | HexagonNewValueJump.cpp | 153 if (II->getOperand(i).isReg() && in INITIALIZE_PASS_DEPENDENCY()
508 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && in runOnMachineFunction()
517 isSecondOpReg = MI.getOperand(2).isReg(); in runOnMachineFunction()
551 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && in runOnMachineFunction()
607 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
614 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
669 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction()
672 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
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| D | HexagonSplitDouble.cpp | 156 if (MI->getOperand(1).isReg()) in isFixedInstr()
161 if (MI->getOperand(0).isReg()) in isFixedInstr()
188 if (!Op.isReg()) in isFixedInstr()
237 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
397 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
454 assert(Cond[1].isReg() && "Unexpected Cond vector from AnalyzeBranch"); in collectIndRegsForLoop()
555 if (!Op.isReg()) { in createHalfInstr()
660 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
689 assert(Op0.isReg()); in splitCombine()
700 } else if (Op1.isReg()) { in splitCombine()
[all …]
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 109 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
111 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
116 RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
118 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
209 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
238 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
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| D | LanaiMemAluCombiner.cpp | 185 return ((Op.isReg() && Op.getReg() == Lanai::R0) || in isZeroOperand()
247 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
264 if (AluOffset.isReg()) in insertMergedInstruction()
308 if (Offset.isReg() && Offset.getReg() == Lanai::R0) in isSuitableAluInstr()
319 } else if (Op2.isReg()) { in isSuitableAluInstr()
321 if (Offset.isReg() && Op2.getReg() == Offset.getReg()) in isSuitableAluInstr()
354 if (Offset->isReg() && InstrUsesReg(First, Offset)) in findClosestSuitableAluInstr()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCCodeEmitter.cpp | 182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getDirectBrEncoding()
198 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getHA16Encoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getLO16Encoding()
217 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
233 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
248 if (MO.isReg()) { in getMachineOpValue()
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| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| D | SparcMCCodeEmitter.cpp | 120 if (MO.isReg()) in getMachineOpValue()
147 if (MO.isReg() || MO.isImm()) in getCallTargetOpValue()
182 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
195 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue()
207 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/AsmPrinter/ |
| D | AsmPrinterDwarf.cpp | 217 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { in EmitCFIFrameMove()
225 } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { in EmitCFIFrameMove()
226 assert(Dst.isReg() && "Machine move not supported yet."); in EmitCFIFrameMove()
229 assert(!Dst.isReg() && "Machine move not supported yet."); in EmitCFIFrameMove()
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| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| D | SparcInstPrinter.cpp | 63 if (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
87 || (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
113 if (MO.isReg()) { in printOperand()
153 if (MO.isReg() && MO.getReg() == SP::G0) in printMemOperand()
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