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Searched refs:isSub (Results 1 – 25 of 27) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb2InstrInfo.cpp179 bool isSub = NumBytes < 0; in emitT2RegPlusImmediate() local
180 if (isSub) NumBytes = -NumBytes; in emitT2RegPlusImmediate()
204 if (isSub) { in emitT2RegPlusImmediate()
237 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate()
245 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
258 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
262 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in emitT2RegPlusImmediate()
391 bool isSub = false; in rewriteT2FrameIndex() local
417 isSub = true; in rewriteT2FrameIndex()
436 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex()
[all …]
DThumb1RegisterInfo.cpp100 bool isSub = false; in emitThumbRegPlusImmInReg() local
106 isSub = true; in emitThumbRegPlusImmInReg()
128 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); in emitThumbRegPlusImmInReg()
133 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
173 bool isSub = NumBytes < 0; in emitThumbRegPlusImmediate() local
175 if (isSub) Bytes = -NumBytes; in emitThumbRegPlusImmediate()
189 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
191 } else if (!isSub && BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
211 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
216 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; in emitThumbRegPlusImmediate()
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DARMBaseInstrInfo.cpp164 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; in convertToThreeAddress() local
172 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
179 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) in convertToThreeAddress()
184 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
190 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; in convertToThreeAddress() local
195 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
200 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
1514 bool isSub = NumBytes < 0; in emitARMRegPlusImmediate() local
1515 if (isSub) NumBytes = -NumBytes; in emitARMRegPlusImmediate()
1528 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
[all …]
/external/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp235 bool isSub = NumBytes < 0; in emitT2RegPlusImmediate() local
236 if (isSub) NumBytes = -NumBytes; in emitT2RegPlusImmediate()
260 if (isSub) { in emitT2RegPlusImmediate()
298 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate()
306 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
319 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate()
323 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in emitT2RegPlusImmediate()
459 bool isSub = false; in rewriteT2FrameIndex() local
485 isSub = true; in rewriteT2FrameIndex()
504 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex()
[all …]
DThumbRegisterInfo.cpp131 bool isSub = false; in emitThumbRegPlusImmInReg() local
137 isSub = true; in emitThumbRegPlusImmInReg()
162 int Opc = (isSub) ? ARM::tSUBrr in emitThumbRegPlusImmInReg()
167 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
185 bool isSub = NumBytes < 0; in emitThumbRegPlusImmediate() local
187 if (isSub) Bytes = -NumBytes; in emitThumbRegPlusImmediate()
220 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
226 assert(!isSub && "Thumb1 does not have tSUBrSPi"); in emitThumbRegPlusImmediate()
235 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3; in emitThumbRegPlusImmediate()
243 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8; in emitThumbRegPlusImmediate()
DARMBaseInstrInfo.cpp160 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; in convertToThreeAddress() local
168 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
178 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) in convertToThreeAddress()
188 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
197 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; in convertToThreeAddress() local
202 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
210 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
2012 bool isSub = NumBytes < 0; in emitARMRegPlusImmediate() local
2013 if (isSub) NumBytes = -NumBytes; in emitARMRegPlusImmediate()
2026 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
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/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h410 bool isSub = Opc == sub; variable
411 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
444 bool isSub = Opc == sub; variable
445 return ((int)isSub << 8) | Offset | (IdxMode << 9);
493 bool isSub = Opc == sub; in getAM5Opc() local
494 return ((int)isSub << 8) | Offset; in getAM5Opc()
516 bool isSub = Opc == sub; in getAM5FP16Opc() local
517 return ((int)isSub << 8) | Offset; in getAM5FP16Opc()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h409 bool isSub = Opc == sub; variable
410 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
443 bool isSub = Opc == sub; variable
444 return ((int)isSub << 8) | Offset | (IdxMode << 9);
492 bool isSub = Opc == sub; in getAM5Opc() local
493 return ((int)isSub << 8) | Offset; in getAM5Opc()
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZFrameLowering.cpp70 bool isSub = NumBytes < 0; in emitSPUpdate() local
71 uint64_t Offset = isSub ? -NumBytes : NumBytes; in emitSPUpdate()
87 .addReg(SystemZ::R15D).addImm(isSub ? -ThisVal : ThisVal); in emitSPUpdate()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FrameLowering.cpp146 bool isSub = NumBytes < 0; in emitSPUpdate() local
147 uint64_t Offset = isSub ? -NumBytes : NumBytes; in emitSPUpdate()
148 unsigned Opc = isSub ? in emitSPUpdate()
158 unsigned Reg = isSub in emitSPUpdate()
162 Opc = isSub in emitSPUpdate()
166 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); in emitSPUpdate()
167 if (isSub) in emitSPUpdate()
178 if (isSub) in emitSPUpdate()
DX86ISelDAGToDAG.cpp1363 bool isInc = false, isDec = false, isSub = false, isCN = false; in SelectAtomicLoadAdd() local
1375 isSub = true; in SelectAtomicLoadAdd()
1381 isSub = true; in SelectAtomicLoadAdd()
1394 else if (isSub) { in SelectAtomicLoadAdd()
1411 else if (isSub) { in SelectAtomicLoadAdd()
1434 else if (isSub) { in SelectAtomicLoadAdd()
1457 else if (isSub) { in SelectAtomicLoadAdd()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp324 bool isSub = OffImm < 0; in printThumbLdrLabelOperand() local
329 if (isSub) { in printThumbLdrLabelOperand()
1230 bool isSub = OffImm < 0; in printAddrModeImm12Operand() local
1234 if (isSub) { in printAddrModeImm12Operand()
1254 bool isSub = OffImm < 0; in printT2AddrModeImm8Operand() local
1258 if (isSub) { in printT2AddrModeImm8Operand()
1283 bool isSub = OffImm < 0; in printT2AddrModeImm8s4Operand() local
1290 if (isSub) { in printT2AddrModeImm8s4Operand()
/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp253 bool isSub = NumBytes < 0; in emitSPUpdate() local
254 uint64_t Offset = isSub ? -NumBytes : NumBytes; in emitSPUpdate()
265 if (isSub && !isEAXLiveIn(MBB)) in emitSPUpdate()
274 Opc = isSub in emitSPUpdate()
289 unsigned Reg = isSub in emitSPUpdate()
293 unsigned Opc = isSub in emitSPUpdate()
297 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); in emitSPUpdate()
298 if (isSub) in emitSPUpdate()
308 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue); in emitSPUpdate()
309 if (isSub) in emitSPUpdate()
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1309 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1318 let Inst{30} = isSub;
1326 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1328 : BaseBaseAddSubCarry<isSub, regtype, asm,
1331 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1333 : BaseBaseAddSubCarry<isSub, regtype, asm,
1339 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1341 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1345 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1351 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
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DAArch64InstrInfo.cpp2395 bool isSub = Offset < 0; in emitFrameOffset() local
2396 if (isSub) in emitFrameOffset()
2412 Opc = isSub ? AArch64::SUBSXri : AArch64::ADDSXri; in emitFrameOffset()
2414 Opc = isSub ? AArch64::SUBXri : AArch64::ADDXri; in emitFrameOffset()
/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/
DInstCombine.h353 bool isSub, Instruction &I);
DInstCombineAndOrXor.cpp408 ConstantInt *Mask, bool isSub, in FoldLogicalPlusAnd() argument
448 if (isSub) in FoldLogicalPlusAnd()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp849 bool isSub = OffImm < 0; in printAddrModeImm12Operand() local
853 if (isSub) in printAddrModeImm12Operand()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV5.td695 class T_sfmpy_acc <bit isSub, bit isLib>
698 "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
713 let Inst{5} = isSub;
DHexagonInstrInfo.td1046 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
1048 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
1060 let Inst{21} = isSub;
/external/llvm/lib/Transforms/InstCombine/
DInstCombineInternal.h561 bool isSub, Instruction &I);
DInstCombineAndOrXor.cpp359 ConstantInt *Mask, bool isSub, in FoldLogicalPlusAnd() argument
399 if (isSub) in FoldLogicalPlusAnd()
/external/valgrind/VEX/priv/
Dguest_arm64_toIR.c2406 Bool isSub = INSN(30,30) == 1; in dis_ARM64_data_processing_immediate() local
2412 const HChar* nm = isSub ? "sub" : "add"; in dis_ARM64_data_processing_immediate()
2424 assign(res, binop(isSub ? Iop_Sub64 : Iop_Add64, in dis_ARM64_data_processing_immediate()
2428 setFlags_ADD_SUB(True/*is64*/, isSub, argL, argR); in dis_ARM64_data_processing_immediate()
2442 assign(res, binop(isSub ? Iop_Sub32 : Iop_Add32, in dis_ARM64_data_processing_immediate()
2446 setFlags_ADD_SUB(False/*!is64*/, isSub, argL, argR); in dis_ARM64_data_processing_immediate()
3097 Bool isSub = INSN(30,30) == 1; in dis_ARM64_data_processing_register() local
3150 assign(res, binop(isSub ? Iop_Sub64 : Iop_Add64, in dis_ARM64_data_processing_register()
3155 setFlags_ADD_SUB(True/*is64*/, isSub, argL, argR); in dis_ARM64_data_processing_register()
3166 setFlags_ADD_SUB(False/*!is64*/, isSub, argL32, argR32); in dis_ARM64_data_processing_register()
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Dguest_arm_toIR.c18653 UInt isSub = INSN0(9,9); in disInstr_THUMB_WRK() local
18658 putIRegT(rD, binop(isSub ? Iop_Sub32 : Iop_Add32, in disInstr_THUMB_WRK()
18661 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK()
18663 DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3); in disInstr_THUMB_WRK()
18674 UInt isSub = INSN0(9,9); in disInstr_THUMB_WRK() local
18679 putIRegT( rD, binop(isSub ? Iop_Sub32 : Iop_Add32, in disInstr_THUMB_WRK()
18682 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD, in disInstr_THUMB_WRK()
18684 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM); in disInstr_THUMB_WRK()
18813 UInt isSub = INSN0(11,11); in disInstr_THUMB_WRK() local
18820 putIRegT( rN, binop(isSub ? Iop_Sub32 : Iop_Add32, in disInstr_THUMB_WRK()
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/external/clang/lib/CodeGen/
DCGExprScalar.cpp2539 bool isSub=false) { in tryEmitFMulAdd() argument
2560 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, false, isSub); in tryEmitFMulAdd()
2565 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub, false); in tryEmitFMulAdd()

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