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Searched refs:LSL (Results 1 – 25 of 42) sorted by relevance

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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Dsp-pc-validations-bad.s11 ldr r0,[r1,pc, LSL #2] @ Unpredictable
12 ldr r0,[r1,pc, LSL #2]! @ ditto
13 ldr r0,[r1],pc, LSL #2 @ ditto
14 ldr r0,[pc,r1, LSL #2]! @ ditto
15 ldr r0,[pc],r1, LSL #2 @ ditto
27 ldrb pc,[r0,r1, LSL #2] @ Unpredictable
28 ldrb pc,[r0,r1, LSL #2]! @ ditto
29 ldrb pc,[r0],r1, LSL #2 @ ditto
30 ldrb r0,[r1,pc, LSL #2] @ ditto
31 ldrb r0,[r1,pc, LSL #2]! @ ditto
[all …]
Daddthumb2err.l2 [^:]*:9: Error: shift value over 3 not allowed in thumb mode -- `add sp,sp,r0,LSL#4'
4 [^:]*:11: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ASR#3'
6 [^:]*:13: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,RRX'
8 [^:]*:15: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,LSR#3'
10 [^:]*:17: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ROR#3'
12 [^:]*:19: Error: shift value over 3 not allowed in thumb mode -- `sub sp,sp,r0,LSL#4'
14 [^:]*:21: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ASR#3'
16 [^:]*:23: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,RRX'
18 [^:]*:25: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,LSR#3'
20 [^:]*:27: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ROR#3'
Dsp-pc-validations-bad-t.s45 LOADw [r0, r1, LSL #2]
69 ldrb.w pc,[r0,r1,LSL #1] @ => PLD
71 ldrb.w r2,[r0,pc,LSL #2] @ BadReg
72 ldrb.w r2,[r0,sp,LSL #2] @ ditto
152 ldrh.w pc,[r0,r1,LSL #1] @ => Unallocated memory hints
153 ldrh.w sp,[r0,r1,LSL #1] @ Unpredictable
154 ldrh.w r2,[r0,pc,LSL #1] @ ditto
155 ldrh.w r2,[r0,sp,LSL #1] @ ditto
182 ldrsb.w pc, [r0, r1, LSL #2] @ => PLI
183 @ldrsb.w r0, [pc, r0, LSL #2] => LDRSB (literal)
[all …]
Dsp-pc-validations-bad.l2 [^:]*:11: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1,pc,LSL#2\]'
4 [^:]*:13: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1\],pc,LSL#2'
6 [^:]*:15: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[pc\],r1,LSL#2'
12 [^:]*:27: Error: r15 not allowed here -- `ldrb pc,\[r0,r1,LSL#2\]'
14 [^:]*:29: Error: r15 not allowed here -- `ldrb pc,\[r0\],r1,LSL#2'
16 [^:]*:31: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1,pc,LSL#2\]!'
18 [^:]*:33: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc,r1,LSL#2\]!'
22 [^:]*:39: Error: r15 not allowed here -- `ldrbt pc,\[r0\],r1,LSL#4'
24 [^:]*:41: Error: cannot use register index with PC-relative addressing -- `ldrbt r0,\[r1\],pc,LSL#4'
102 [^:]*:159: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],r1,LSL#4'
[all …]
Daddthumb2err.s9 add sp, sp, r0, LSL #4
14 adds sp, sp, r0, LSL #4
19 sub sp, sp, r0, LSL #4
24 subs sp, sp, r0, LSL #4
Dsp-pc-validations-bad-t.l16 [^:]*:45: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL#2\]'
32 [^:]*:69: Error: r15 not allowed here -- `ldrb.w pc,\[r0,r1,LSL#1\]'
34 [^:]*:71: Error: r15 not allowed here -- `ldrb.w r2,\[r0,pc,LSL#2\]'
96 [^:]*:152: Error: r15 not allowed here -- `ldrh.w pc,\[r0,r1,LSL#1\]'
98 [^:]*:154: Error: r15 not allowed here -- `ldrh.w r2,\[r0,pc,LSL#1\]'
118 [^:]*:184: Error: r13 not allowed here -- `ldrsb.w sp,\[r0,r1,LSL#2\]'
120 [^:]*:186: Error: r13 not allowed here -- `ldrsb.w r2,\[r0,sp,LSL#2\]'
138 [^:]*:215: Error: r13 not allowed here -- `ldrsh.w sp,\[r0,r1,LSL#3\]'
140 [^:]*:217: Error: r15 not allowed here -- `ldrsh.w r0,\[r1,pc,LSL#3\]'
240 [^:]*:355: Error: r15 not allowed here -- `strh.w pc,\[r0,r1,LSL#2\]'
[all …]
Darchv6.s13 pkhbt r2, r5, r8, LSL #3
14 pkhbtal r2, r5, r8, LSL #3
15 pkhbteq r2, r5, r8, LSL #3
122 ssat r1, #1, r2, LSL #2
195 usat r1, #15, r2, LSL #4
200 usatle r1, #15, r2, LSL #4
Dthumb2_bad_reg.s137 @ LSL (immediate)
142 @ LSL (register)
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/
Dmovi.s73 all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, \amount
74 all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, \amount
75 all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, \amount
76 all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, \amount
89 all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, \amount
90 all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, \amount
91 all_8bit_imm_movi_sft v7.\T, 128, 191, LSL, \amount
92 all_8bit_imm_movi_sft v7.\T, 192, 255, LSL, \amount
105 all_8bit_imm_movi_sft v7.\T, 0, 63, LSL, 0
106 all_8bit_imm_movi_sft v7.\T, 64, 127, LSL, 0
[all …]
Dillegal-2.s13 add wsp, w0, #0xfff0, LSL #12
14 add wsp, w0, #0xfff0, LSL #0
15 add wsp, w0, u16, LSL #12
16 add wsp, w0, u16, LSL #0
Daddsub.s33 .ifnc \extend, LSL
110 do_addsub_ext \type, \op, \Rn, \reg, LSL, \amount
160 .irp shift, LSL, LSR, ASR
Dillegal.s481 add x0, x1, #20, LSL #16
484 add x0, x1, #20, LSL
Dillegal.l509 [^:]*:481: Error: .*`add x0,x1,#20,LSL#16'
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/epiphany/
Dregression.s29 LSL R0,R0,#2 ; //Create 00020000
172 LSLLAB: LSL R63,R3,#0x2 ; //3<<2=12
177 LSLILAB: LSL R63,R3,R2 ; //3<<2=12
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/metag/
Dmetacore21.s1756 LSL D0Re0,D0.7,D0.7
1759 LSL D1Re0,D1.7,D1.7
1762 LSL D0Re0,D0.7,#0xf
1765 LSL D0.7,D0.7,#0x1f define
1768 LSL D1.7,D1Re0,#0x10 define
1771 LSL TTEXEC,D0Re0,D0Re0
1773 LSL PC,D0Re0,D0.7
1781 LSL PCX,D0Re0,D0Re0
1784 LSL PCX,D0.7,D0Re0
1789 LSL TXMASKI,D0Re0,D0.7
[all …]
Dmetafpu21.s1258 F LSL FX.1,D0.7,D0.7
1261 F LSL FX.3,D0.7,D0.7
1264 F LSL FX.5,D0.7,D0.7
1267 F LSL FX.10,D0.7,D0.7
1270 F LSL FX.0,D1.7,D1.7
1273 F LSL FX.2,D1.7,D1.7
1276 F LSL FX.4,D1.7,D1.7
1279 F LSL FX.7,D1.7,D1.7
1282 F LSL FX.15,D1.7,D1.7
1285 F LSL FX.1,D0Re0,#0x10
[all …]
Dmetacore21.d1764 .*: 5001ce00 LSL D0Re0,D0\.7,D0\.7
1767 .*: 5101ce00 LSL D1Re0,D1\.7,D1\.7
1770 .*: 5201de00 LSL D0Re0,D0\.7,#0xf
1773 .*: 5239fe00 LSL D0\.7,D0\.7,#0x1f
1776 .*: 53382000 LSL D1\.7,D1Re0,#0x10
1779 .*: 54000030 LSL TTEXEC,D0Re0,D0Re0
1781 .*: 54000e2a LSL PC,D0Re0,D0\.7
1789 .*: 5408002a LSL PCX,D0Re0,D0Re0
1792 .*: 5409c02a LSL PCX,D0\.7,D0Re0
1797 .*: 54180e2e LSL TXMASKI,D0Re0,D0\.7
[all …]
Dmetacore12.s2901 LSL D0Re0,D0.7,D0Re0
2904 LSL D1Re0,D1.7,D1Re0
2907 LSL D0Re0,D0Re0,#0x1f
2910 LSL D0.7,D0.7,#0x10 define
2913 LSL D1.7,D1Re0,#0xf define
2918 LSL PC,D0Re0,D0.7
2920 LSL TXENABLE,D0.7,D0Re0
2940 LSL RAM8X32,D0.7,D0Re0
2943 LSL RABZ,D0.7,D0Re0
2946 LSL TXIDLECYC,D0Re0,D0.7
[all …]
Dmetafpu21.d1266 .*: 5409ce32 F LSL FX\.1,D0\.7,D0\.7
1269 .*: 5419ce32 F LSL FX\.3,D0\.7,D0\.7
1272 .*: 5429ce32 F LSL FX\.5,D0\.7,D0\.7
1275 .*: 5451ce32 F LSL FX\.10,D0\.7,D0\.7
1278 .*: 5501ce32 F LSL FX\.0,D1\.7,D1\.7
1281 .*: 5511ce32 F LSL FX\.2,D1\.7,D1\.7
1284 .*: 5521ce32 F LSL FX\.4,D1\.7,D1\.7
1287 .*: 5539ce32 F LSL FX\.7,D1\.7,D1\.7
1290 .*: 5579ce32 F LSL FX\.15,D1\.7,D1\.7
1293 .*: 56082032 F LSL FX\.1,D0Re0,#0x10
[all …]
/toolchain/binutils/binutils-2.27/opcodes/
Daarch64-tbl.h1302 QLF2(V_2S, LSL), \
1303 QLF2(V_4S, LSL), \
1316 QLF2(V_4H, LSL), \
1317 QLF2(V_8H, LSL), \
1330 QLF2(V_8B, LSL), \
1331 QLF2(V_16B, LSL), \
/toolchain/binutils/binutils-2.27/cpu/
Dmt.cpu277 LSL LSR ASR - - - - -
814 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
/toolchain/binutils/binutils-2.27/opcodes/po/
Dfi.po185 msgid "'LSL' operator not allowed"
186 msgstr "’LSL’-operaattori ei ole sallittu"
Dfr.po188 msgid "'LSL' operator not allowed"
189 msgstr "opérateur LSL interdit"
Dde.po184 msgid "'LSL' operator not allowed"
185 msgstr "LSL-Operator ist hier nicht erlaubt"
Dopcodes.pot180 msgid "'LSL' operator not allowed"

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