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/toolchain/binutils/binutils-2.27/binutils/testsuite/binutils-all/
Dcompress.exp85 set src1 ${compressedfile}.o
87 set status [remote_exec build cmp "${src1} ${src2}"]
107 set src1 ${testfile}.o
109 set status [remote_exec build cmp "${src1} ${src2}"]
203 set src1 ${testfile}empty.o
205 set status [remote_exec build cmp "${src1} ${src2}"]
238 set src1 ${compressedfile}gabi.o
240 set status [remote_exec build cmp "${src1} ${src2}"]
258 set src1 ${compressedfile2}gabi.o
260 set status [remote_exec build cmp "${src1} ${src2}"]
[all …]
Dupdate-section.exp56 set src1 "tmpdir/${file1}"
58 set status [remote_exec build cmp "${src1} ${src2}"]
Dobjcopy.exp64 set src1 tmpdir/bintest.o
66 remote_upload host $tempfile $src1
69 set src1 ${tempfile}
72 set status [remote_exec build cmp "${src1} ${src2}"]
/toolchain/binutils/binutils-2.27/include/opcode/
Dtic6x-opcode-table.h138 FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)),
151 ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
163 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
168 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
173 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
178 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
183 ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
188 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
193 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
199 ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
[all …]
Dtic6x-insn-formats.h71 CFLDS5(FLD(s, 1, 1), FLD(op, 7, 6), FLD(src1, 13, 5), FLD(src2, 18, 5),
74 CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
134 FLD(t, 12, 1), FLD(src1, 13, 3)))
138 FLD(t, 12, 1), FLD(src1, 13, 3)))
142 FLD(t, 12, 1), FLD(src1, 13, 3)))
146 FLD(t, 12, 1), FLD(src1, 13, 3)))
150 FLD(t, 12, 1), FLD(src1, 13, 3)))
154 FLD(t, 12, 1), FLD(src1, 13, 3)))
158 FLD(t, 12, 1), FLD(src1, 13, 3)))
162 FLD(t, 12, 1), FLD(src1, 13, 3)))
[all …]
Dm88k.h112 src1: SOURCE1, member
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic6x/
Dinsns16-d-unit.s24 dx2op: ; op = 0 | ADD (.unit) src1, src2, dst (src1 = dst)
25 ; op = 1 | SUB (.unit) src1, src2, dst (src1 = dst, dst = src1 - src2
/toolchain/binutils/binutils-2.27/opcodes/
Dbfin-dis.c557 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf) in decode_multfunc() argument
567 s1 = dregs_hi (src1); in decode_multfunc()
569 s1 = dregs_lo (src1); in decode_multfunc()
578 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf) in decode_macfunc() argument
604 decode_multfunc (h0, h1, src0, src1, outf); in decode_macfunc()
1652 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask); in decode_COMP3op_0() local
1654 if (opc == 5 && src1 == src0) in decode_COMP3op_0()
1667 OUTS (outf, dregs (src1)); in decode_COMP3op_0()
1675 OUTS (outf, dregs (src1)); in decode_COMP3op_0()
1683 OUTS (outf, dregs (src1)); in decode_COMP3op_0()
[all …]
Di960-dis.c232 int src1; in cobr() local
286 src1 = (word1 >> 19) & 0x1f; in cobr()
291 (*info->fprintf_func) (stream, "%d", src1); in cobr()
293 (*info->fprintf_func) (stream, "%s", reg_names[src1]); in cobr()
DChangeLog-20131110 individual msb and lsb halves in src1 & src2 fields. Discard the
1111 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1112 follow what Ti SDK does in that case as any value in the src1
Darc-opc.c939 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
Dh8500-opc.h151 char flags,src1,src2,dst; member
/toolchain/binutils/binutils-2.27/cpu/
Dm32r.cpu250 ((src1 INT -1) (src2 INT -1)) ; inputs
257 ((src1 INT -1) (src2 INT -1)) ; inputs
280 ((src1 INT) (src2 INT)) ; inputs
316 ((src1 INT -1) (src2 INT -1)) ; inputs
323 ((src1 INT -1) (src2 INT -1)) ; inputs
344 ((src1 INT) (src2 INT)) ; inputs
369 ((src1 INT -1) (src2 INT -1)) ; inputs
376 ((src1 INT -1) (src2 INT -1)) ; inputs
397 ((src1 INT) (src2 INT)) ; inputs
666 ;; The assembler relies upon the fact that dr and src1 are the same field.
[all …]
Dm32c.cpu7155 (define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem)
7156 (dni (.sym op 32 wstr - src1 - src2 - dstgroup)
7157 (.str op 32 wstr "-" src1 "-" src2 "-" dstgroup "-" xmode)
7159 (.str op wstr " #${" src1 "},#${" src2 "},${dst32-" dstgroup "-" xmode "}")
7161 (sem xmode src1 src2 (.sym dst32- dstgroup - xmode))
7255 (define-pmacro (add-sem mode src1 dst)
7257 (set result (add mode src1 dst))
7258 (set obit (add-oflag mode src1 dst 0))
7259 (set cbit (add-cflag mode src1 dst 0))
7439 (define-pmacro (and-sem mode src1 dst)
[all …]
Dxc16x.cpu107 ((src1 INT -1) (src2 INT -1)) ; inputs
546 (dnop src1 "source register 1" () h-gr f-r1)
1115 "mul $src1,$src2"
1116 (+ OP1_0 OP2_11 src1 src2)
1123 "mulu $src1,$src2"
1124 (+ OP1_1 OP2_11 src1 src2)
2940 "cmp $src1,$src2"
2941 (+ OP1_4 OP2_0 src1 src2)
2942 (set condbit (lt HI src1 src2))
2966 (cmp1 cmpri cmp OP1_4 OP2_8 src1 uimm3 HI)
Dcris.cpu3387 ((DI src1) (DI src2) (DI tmpr))
3388 (set src1 (ext DI (trunc BWD Rs)))
3390 (set tmpr (mul src1 src2))
3393 (setf-arit DI muls src1 src2 tmpr cbit)))
3407 ((DI src1) (DI src2) (DI tmpr))
3408 (set src1 (zext DI (trunc BWD Rs)))
3410 (set tmpr (mul src1 src2))
3413 (setf-arit DI mulu src1 src2 tmpr cbit)))
Dfrv.cpu9319 (define-pmacro (media-pack src1 src2 targ offset)
9321 (set (halfword hi targ offset) (halfword lo src1 offset))
/toolchain/binutils/binutils-2.27/gas/config/
Dtc-bfin.c1174 REG_T dst, REG_T src0, REG_T src1, int w0) in bfin_gen_dsp32mac() argument
1199 ASSIGN_R (src1); in bfin_gen_dsp32mac()
1207 REG_T dst, REG_T src0, REG_T src1, int w0) in bfin_gen_dsp32mult() argument
1230 ASSIGN_R (src1); in bfin_gen_dsp32mult()
1237 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1) in bfin_gen_dsp32alu() argument
1249 ASSIGN_R (src1); in bfin_gen_dsp32alu()
1256 REG_T src1, int sop, int HLs) in bfin_gen_dsp32shift() argument
1266 ASSIGN_R (src1); in bfin_gen_dsp32shift()
1273 REG_T src1, int sop, int HLs) in bfin_gen_dsp32shiftimm() argument
1283 ASSIGN_R (src1); in bfin_gen_dsp32shiftimm()
[all …]
Dbfin-parse.y29 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \ argument
30 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
32 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \ argument
34 dst, src0, src1, w0)
36 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \ argument
38 dst, src0, src1, w0)
40 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \ argument
41 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
43 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \ argument
44 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
[all …]
Dtc-i960.c1930 int opcode, src1, src2, m1, s2; in relax_cobr() local
1942 src1 = (instr >> 19) & 0x1f; in relax_cobr()
1950 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14); in relax_cobr()