Home
last modified time | relevance | path

Searched refs:AND_V (Results 1 – 21 of 21) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCPseudoLowering.inc17 TmpInst.setOpcode(Mips::AND_V);
33 TmpInst.setOpcode(Mips::AND_V);
49 TmpInst.setOpcode(Mips::AND_V);
DMipsGenMCCodeEmitter.inc618 UINT64_C(2013265950), // AND_V
7180 case Mips::AND_V:
8344 Feature_HasStdEnc | Feature_HasMSA | 0, // AND_V = 605
DMipsGenAsmWriter.inc1833 268459710U, // AND_V
4464 0U, // AND_V
DMipsGenFastISel.inc1398 return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenGlobalISel.inc2203 …i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA1…
2204 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
DMipsGenInstrInfo.inc620 AND_V = 605,
4665 …05, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #605 = AND_V
DMipsGenDisassemblerTables.inc5280 /* 12545 */ MCD::OPC_Decode, 221, 4, 250, 1, // Opcode: AND_V
DMipsGenAsmMatcher.inc5187 …{ 476 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Featur…
DMipsGenDAGISel.inc15397 /* 28227*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND_V), 0,
15400 … // Dst: (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
/external/v8/src/mips/
Dconstants-mips.h789 AND_V = (((0U << 2) + 0) << 21), enumerator
Ddisasm-mips.cc2579 case AND_V: in DecodeTypeMsaVec()
Dassembler-mips.cc3352 V(and_v, AND_V) \
Dsimulator-mips.cc5736 case AND_V: in DecodeTypeMsaVec()
/external/v8/src/mips64/
Dconstants-mips64.h823 AND_V = (((0U << 2) + 0) << 21), enumerator
Ddisasm-mips64.cc2893 case AND_V: in DecodeTypeMsaVec()
Dassembler-mips64.cc3669 V(and_v, AND_V) \
Dsimulator-mips64.cc5960 case AND_V: in DecodeTypeMsaVec()
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td2742 def AND_V : AND_V_ENC, AND_V_DESC;
2744 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2748 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2752 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td2749 def AND_V : AND_V_ENC, AND_V_DESC;
2751 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2755 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2759 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc96 33577807U, // AND_V
1810 0U, // AND_V
DMipsGenDisassemblerTables.inc2821 /* 9805 */ MCD_OPC_Decode, 79, 114, // Opcode: AND_V