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Searched refs:BSEL_V (Results 1 – 21 of 21) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCPseudoLowering.inc103 TmpInst.setOpcode(Mips::BSEL_V);
122 TmpInst.setOpcode(Mips::BSEL_V);
141 TmpInst.setOpcode(Mips::BSEL_V);
160 TmpInst.setOpcode(Mips::BSEL_V);
179 TmpInst.setOpcode(Mips::BSEL_V);
DMipsGenMCCodeEmitter.inc833 UINT64_C(2025848862), // BSEL_V
7457 case Mips::BSEL_V:
8559 Feature_HasStdEnc | Feature_HasMSA | 0, // BSEL_V = 820
DMipsGenAsmWriter.inc2048 285236941U, // BSEL_V
4679 24U, // BSEL_V
DMipsGenInstrInfo.inc835 BSEL_V = 820,
4880 …0, 4, 1, 4, 504, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #820 = BSEL_V
DMipsGenDisassemblerTables.inc5298 /* 12635 */ MCD::OPC_Decode, 180, 6, 254, 1, // Opcode: BSEL_V
DMipsGenAsmMatcher.inc5464 …{ 1606 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmR…
DMipsGenDAGISel.inc28772 /* 54032*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSEL_V), 0,
28775 …// Dst: (BSEL_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA…
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1173 // (BSEL_V cond, if_clear, if_set)
1723 // Note that vselect and BSEL_V treat the condition operand the opposite way
1726 // (BSEL_V cond, if_clear, if_set)
1739 // Note that vselect and BSEL_V treat the condition operand the opposite way
1742 // (BSEL_V cond, if_clear, if_set)
2843 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2848 // Note that vselect and BSEL_V treat the condition operand the opposite way
2851 // (BSEL_V cond, if_clear, if_set)
2852 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1171 // (BSEL_V cond, if_clear, if_set)
1721 // Note that vselect and BSEL_V treat the condition operand the opposite way
1724 // (BSEL_V cond, if_clear, if_set)
1737 // Note that vselect and BSEL_V treat the condition operand the opposite way
1740 // (BSEL_V cond, if_clear, if_set)
2850 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2855 // Note that vselect and BSEL_V treat the condition operand the opposite way
2858 // (BSEL_V cond, if_clear, if_set)
2859 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
DMipsScheduleP5600.td289 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>;
DMipsScheduleGeneric.td922 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>;
/external/v8/src/mips/
Dconstants-mips.h795 BSEL_V = (((1U << 2) + 2) << 21), enumerator
Ddisasm-mips.cc2597 case BSEL_V: in DecodeTypeMsaVec()
Dsimulator-mips.cc5730 if (opcode == BMNZ_V || opcode == BMZ_V || opcode == BSEL_V) { in DecodeTypeMsaVec()
5754 case BSEL_V: in DecodeTypeMsaVec()
Dassembler-mips.cc3358 V(bsel_v, BSEL_V)
/external/v8/src/mips64/
Dconstants-mips64.h829 BSEL_V = (((1U << 2) + 2) << 21), enumerator
Ddisasm-mips64.cc2911 case BSEL_V: in DecodeTypeMsaVec()
Dsimulator-mips64.cc5954 if (opcode == BMNZ_V || opcode == BMZ_V || opcode == BSEL_V) { in DecodeTypeMsaVec()
5978 case BSEL_V: in DecodeTypeMsaVec()
Dassembler-mips64.cc3675 V(bsel_v, BSEL_V)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc306 2183158622U, // BSEL_V
2020 0U, // BSEL_V
DMipsGenDisassemblerTables.inc2839 /* 9876 */ MCD_OPC_Decode, 161, 2, 118, // Opcode: BSEL_V