| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.h | 190 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
192 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
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| D | MipsISelLowering.cpp | 876 unsigned Size, unsigned BinOpcode, in EmitAtomicBinary() argument
929 } else if (BinOpcode) { in EmitAtomicBinary()
931 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); in EmitAtomicBinary()
948 unsigned Size, unsigned BinOpcode, in EmitAtomicBinaryPartword() argument
1058 } else if (BinOpcode) { in EmitAtomicBinaryPartword()
1061 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); in EmitAtomicBinaryPartword()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 581 unsigned Size, unsigned BinOpcode,
586 unsigned BinOpcode,
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| D | MipsISelLowering.cpp | 1104 unsigned BinOpcode, in emitAtomicBinary() argument
1182 } else if (BinOpcode) { in emitAtomicBinary()
1184 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); in emitAtomicBinary()
1227 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, in emitAtomicBinaryPartword() argument
1355 } else if (BinOpcode) { in emitAtomicBinaryPartword()
1358 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); in emitAtomicBinaryPartword()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 307 unsigned BinOpcode) const;
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| D | PPCISelLowering.cpp | 4653 bool is64bit, unsigned BinOpcode) const { in EmitAtomicBinary()
4678 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary()
4697 if (BinOpcode) in EmitAtomicBinary()
4698 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); in EmitAtomicBinary()
4716 unsigned BinOpcode) const { in EmitPartwordAtomicBinary()
4762 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
4819 if (BinOpcode) in EmitPartwordAtomicBinary()
4820 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) in EmitPartwordAtomicBinary()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 575 unsigned BinOpcode, unsigned BitSize,
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| D | SystemZISelLowering.cpp | 5312 MachineInstr &MI, MachineBasicBlock *MBB, unsigned BinOpcode, in emitAtomicLoadBinary() argument
5347 unsigned NewVal = (BinOpcode || IsSubWord ? in emitAtomicLoadBinary()
5384 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp) in emitAtomicLoadBinary()
5398 } else if (BinOpcode) in emitAtomicLoadBinary()
5400 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal) in emitAtomicLoadBinary()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 502 unsigned BinOpcode) const;
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| D | ARMISelLowering.cpp | 5148 unsigned Size, unsigned BinOpcode) const { in EmitAtomicBinary()
5200 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); in EmitAtomicBinary()
5219 if (BinOpcode) { in EmitAtomicBinary()
5221 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) in EmitAtomicBinary()
5222 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). in EmitAtomicBinary()
5225 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). in EmitAtomicBinary()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 629 unsigned BinOpcode, unsigned BitSize,
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| D | SystemZISelLowering.cpp | 6287 MachineInstr &MI, MachineBasicBlock *MBB, unsigned BinOpcode, in emitAtomicLoadBinary() argument
6322 unsigned NewVal = (BinOpcode || IsSubWord ? in emitAtomicLoadBinary()
6358 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp).addReg(RotatedOldVal).add(Src2); in emitAtomicLoadBinary()
6371 } else if (BinOpcode) in emitAtomicLoadBinary()
6373 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal) in emitAtomicLoadBinary()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 588 unsigned BinOpcode) const;
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| D | PPCISelLowering.cpp | 8421 unsigned BinOpcode) const { in EmitAtomicBinary()
8469 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary()
8487 if (BinOpcode) in EmitAtomicBinary()
8488 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); in EmitAtomicBinary()
8506 unsigned BinOpcode) const { in EmitPartwordAtomicBinary()
8509 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode); in EmitPartwordAtomicBinary()
8553 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
8610 if (BinOpcode) in EmitPartwordAtomicBinary()
8611 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) in EmitPartwordAtomicBinary()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1873 auto BinOpcode = BO->getOpcode(); in foldBinOpIntoSelect() local
1874 assert((BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || in foldBinOpIntoSelect()
1875 BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || in foldBinOpIntoSelect()
1876 BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || in foldBinOpIntoSelect()
1877 BinOpcode == ISD::UREM || BinOpcode == ISD::AND || in foldBinOpIntoSelect()
1878 BinOpcode == ISD::OR || BinOpcode == ISD::XOR || in foldBinOpIntoSelect()
1879 BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || in foldBinOpIntoSelect()
1880 BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || in foldBinOpIntoSelect()
1881 BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || in foldBinOpIntoSelect()
1882 BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && in foldBinOpIntoSelect()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 696 unsigned BinOpcode,
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| D | PPCISelLowering.cpp | 9674 unsigned BinOpcode, in EmitAtomicBinary() argument
9728 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary()
9757 if (BinOpcode) in EmitAtomicBinary()
9758 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); in EmitAtomicBinary()
9794 unsigned BinOpcode, in EmitPartwordAtomicBinary() argument
9799 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode, in EmitPartwordAtomicBinary()
9850 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
9908 if (BinOpcode) in EmitPartwordAtomicBinary()
9909 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) in EmitPartwordAtomicBinary()
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