| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 61 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
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| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 352 CVT_L_S = 4, enumerator
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| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 385 CVT_L_S = 4, enumerator
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| /external/v8/src/mips/ |
| D | constants-mips.h | 623 CVT_L_S = ((4U << 3) + 5), enumerator
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| D | assembler-mips.cc | 2960 GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S); in cvt_l_s()
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| D | simulator-mips.cc | 3527 case CVT_L_S: { in DecodeTypeRegisterSRsType()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 95 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 95 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 654 CVT_L_S = ((4U << 3) + 5), enumerator
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| D | assembler-mips64.cc | 3349 GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S); in cvt_l_s()
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| D | simulator-mips64.cc | 2816 case CVT_L_S: { in DecodeTypeRegisterSRsType()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 95 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 93 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 93 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 95 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 311 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 421 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 475 22772U, // CVT_L_S
2189 0U, // CVT_L_S
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| D | MipsGenDisassemblerTables.inc | 919 /* 2082 */ MCD_OPC_Decode, 202, 3, 75, // Opcode: CVT_L_S
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1055 UINT64_C(1174405157), // CVT_L_S
3154 case Mips::CVT_L_S:
8781 …nc | Feature_HasMips3_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_L_S = 1042
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| D | MipsGenAsmWriter.inc | 2270 23543U, // CVT_L_S
4901 0U, // CVT_L_S
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| D | MipsGenInstrInfo.inc | 1057 CVT_L_S = 1042,
5102 … 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1042 = CVT_L_S
10062 { Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM },
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| D | MipsGenDisassemblerTables.inc | 3384 /* 3021 */ MCD::OPC_Decode, 146, 8, 209, 1, // Opcode: CVT_L_S
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| D | MipsGenAsmMatcher.inc | 5879 …{ 3035 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Fe…
|