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Searched refs:DCLZ (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMips64InstrInfo.td182 def DCLZ : CountLeading64<0x24, "dclz",
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_64.c225 …FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | TA(EQUAL_FLAG) | DA(EQUAL_FLAG), EQUA… in emit_single_op()
227 FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | T(dst) | D(dst), DR(dst))); in emit_single_op()
DsljitNativeMIPS_common.c193 #define DCLZ (HI(28) | LO(36)) macro
/external/v8/src/mips64/
Dconstants-mips64.h572 DCLZ = ((4U << 3) + 4), enumerator
1766 case DCLZ: in InstructionType()
Ddisasm-mips64.cc1725 case DCLZ: in DecodeTypeRegisterSPECIAL2()
Dassembler-mips64.cc2840 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, DCLZ); in dclz()
Dsimulator-mips64.cc4141 case DCLZ: in DecodeTypeRegisterSPECIAL2()
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td296 def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64InstrInfo.td342 def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>,
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc551 25247U, // DCLZ
2265 0U, // DCLZ
DMipsGenDisassemblerTables.inc4480 /* 1805 */ MCD_OPC_Decode, 150, 4, 244, 1, // Opcode: DCLZ
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc1184 UINT64_C(1879048228), // DCLZ
4754 case Mips::DCLZ: {
8910 …re_HasStdEnc | Feature_HasMips64 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DCLZ = 1171
DMipsGenAsmWriter.inc2399 26152U, // DCLZ
5030 0U, // DCLZ
DMipsGenFastISel.inc204 return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
DMipsGenInstrInfo.inc1186 DCLZ = 1171,
5231 …171, 2, 1, 4, 90, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1171 = DCLZ
DMipsGenDisassemblerTables.inc6995 /* 984 */ MCD::OPC_Decode, 147, 9, 243, 2, // Opcode: DCLZ
DMipsGenAsmMatcher.inc5917 …{ 3143 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_…
DMipsGenDAGISel.inc12772 /* 23520*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DCLZ), 0,
12775 // Dst: (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)