Searched refs:DSRA32 (Results 1 – 19 of 19) sorted by relevance
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 180 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(24), DR(dst)); in emit_single_op()
195 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(16), DR(dst)); in emit_single_op()
475 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRA32, SRA) | T(dst) | DA(OTHER_FLAG) | SH_IMM(31), OTHER_F… in emit_single_op()
499 EMIT_SHIFT(DSRA, DSRA32, SRA, DSRAV, SRAV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 145 #define DSRA32 (HI(0) | LO(63)) macro
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 121 def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>;
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 547 DSRA32 = ((7U << 3) + 7), enumerator
1323 FunctionFieldToBitNumber(DSRA) | FunctionFieldToBitNumber(DSRA32) |
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| D | disasm-mips64.cc | 1484 case DSRA32: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2228 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA32); in dsra32()
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| D | simulator-mips64.cc | 3756 case DSRA32: in DecodeTypeRegisterSPECIAL()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 76 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 84 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 161 def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 177 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 638 1107312799U, // DSRA32
2352 0U, // DSRA32
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| D | MipsGenDisassemblerTables.inc | 4172 /* 370 */ MCD_OPC_Decode, 237, 4, 232, 1, // Opcode: DSRA32
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1297 UINT64_C(63), // DSRA32
4675 case Mips::DSRA32:
9023 Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRA32 = 1284
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| D | MipsGenAsmWriter.inc | 2512 268452069U, // DSRA32
5143 4U, // DSRA32
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| D | MipsGenAsmMatcher.inc | 6113 …{ 3862 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Fe…
6114 …{ 3862 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Fe…
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| D | MipsGenInstrInfo.inc | 1299 DSRA32 = 1284,
5344 …odeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1284 = DSRA32
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| D | MipsGenDisassemblerTables.inc | 6900 /* 495 */ MCD::OPC_Decode, 132, 10, 236, 2, // Opcode: DSRA32
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4748 TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32, in expandMulO()
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