| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 124 def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 151 def DSRAV : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
579 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
692 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 506 DSRAV = ((2U << 3) + 7), enumerator
1326 FunctionFieldToBitNumber(SRAV) | FunctionFieldToBitNumber(DSRAV) |
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| D | disasm-mips64.cc | 1510 case DSRAV: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2213 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRAV); in dsrav()
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| D | simulator-mips64.cc | 3797 case DSRAV: in DecodeTypeRegisterSPECIAL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 169 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
750 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
938 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 499 EMIT_SHIFT(DSRA, DSRA32, SRA, DSRAV, SRAV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 146 #define DSRAV (HI(0) | LO(23)) macro
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 639 33577872U, // DSRAV
2353 0U, // DSRAV
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| D | MipsGenDisassemblerTables.inc | 4108 /* 76 */ MCD_OPC_Decode, 238, 4, 230, 1, // Opcode: DSRAV
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1298 UINT64_C(23), // DSRAV
4620 case Mips::DSRAV:
9024 Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRAV = 1285
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| D | MipsGenAsmWriter.inc | 2513 268459775U, // DSRAV
5144 0U, // DSRAV
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| D | MipsGenGlobalISel.inc | 12996 …} GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:…
13002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRAV,
13014 …// (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } …
13015 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRAV,
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| D | MipsGenAsmMatcher.inc | 6111 …{ 3857 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_H…
6115 …{ 3869 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_…
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| D | MipsGenDAGISel.inc | 21413 /* 39628*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRAV), 0,
21416 …// Dst: (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$r…
21442 /* 39682*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRAV), 0,
21445 // Dst: (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
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| D | MipsGenInstrInfo.inc | 1300 DSRAV = 1285,
5345 …5, 3, 1, 4, 120, 0, 0x1ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1285 = DSRAV
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| D | MipsGenDisassemblerTables.inc | 6836 /* 159 */ MCD::OPC_Decode, 133, 10, 234, 2, // Opcode: DSRAV
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