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Searched refs:HiReg (Results 1 – 25 of 26) sorted by relevance

12

/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td340 (LoReg (S2_packhl (HiReg $Rs), (LoReg $Rs)))>;
358 (A2_combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
362 (A2_combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
384 (S2_vtrunewh (vmpyh (HiReg $Rs), (HiReg $Rt)),
388 (S2_vtrunewh (vmpyh (HiReg (S2_vsxtbh $Rs)), (HiReg (S2_vsxtbh $Rt))),
401 (A2_combinew (S2_vtrunehb (M5_vmpybsu (HiReg $Rs), (HiReg $Rt))),
406 (A2_combinew (S2_vtrunehb (VMPYB_no_V5 (HiReg $Rs), (HiReg $Rt))),
453 (S2_storeri_io I32:$Rt, 0, (LoReg (S2_packhl (HiReg $Rs),
DHexagonCopyToCombine.cpp783 unsigned HiReg = HiOperand.getReg(); in emitCombineRI() local
791 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
799 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
823 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
834 unsigned HiReg = HiOperand.getReg(); in emitCombineRR() local
842 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
DHexagonFrameLowering.cpp826 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::subreg_hireg); in insertCFIInstructionsAt() local
828 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
DHexagonInstrInfo.td32 def HiReg: OutPatFrag<(ops node:$Rs),
4935 (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2),
4936 (HiReg DoubleRegs:$src3)),
5058 (HiReg $src1),
5061 (LoReg (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2))))),
5063 (HiReg $src1),
5064 (HiReg $src2)),
5065 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2)), 32)
DHexagonIntrinsics.td766 (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>;
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsExpandPseudo.cpp89 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in ExpandBuildPairF64() local
98 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg); in ExpandBuildPairF64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCopyToCombine.cpp812 unsigned HiReg = HiOperand.getReg(); in emitCombineRI() local
820 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
828 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
852 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
863 unsigned HiReg = HiOperand.getReg(); in emitCombineRR() local
880 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
DHexagonPatterns.td117 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
456 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
459 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
475 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
784 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
795 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
814 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
966 (A2_swiz (HiReg $Rss)))>;
1190 (Combinew (S2_clrbit_i (HiReg $Rs), 31),
1193 (Combinew (S2_togglebit_i (HiReg $Rs), 31),
[all …]
DHexagonIntrinsics.td744 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
746 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
788 (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>;
DHexagonFrameLowering.cpp946 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
948 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.cpp268 unsigned &HiReg) const { in splitReg()
272 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
DAVRRegisterInfo.h53 void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2184 unsigned SrcReg, LoReg, HiReg; in Select() local
2189 SrcReg = LoReg = X86::AL; HiReg = X86::AH; in Select()
2193 SrcReg = LoReg = X86::AX; HiReg = X86::DX; in Select()
2197 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select()
2201 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select()
2204 SrcReg = X86::EDX; LoReg = HiReg = 0; in Select()
2207 SrcReg = X86::RDX; LoReg = HiReg = 0; in Select()
2268 if (HiReg == X86::AH && Subtarget->is64Bit() && in Select()
2302 assert(HiReg && "Register for high half is not defined!"); in Select()
2303 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT, in Select()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelDAGToDAG.cpp1884 unsigned LoReg, HiReg; in Select() local
1887 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; in Select()
1888 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; in Select()
1889 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; in Select()
1890 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break; in Select()
1921 if (HiReg == X86::AH && Subtarget->is64Bit() && in Select()
1951 HiReg, NVT, InFlag); in Select()
1984 unsigned LoReg, HiReg, ClrReg; in Select() local
1989 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
1994 LoReg = X86::AX; HiReg = X86::DX; in Select()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2967 unsigned SrcReg, LoReg, HiReg; in Select() local
2972 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select()
2976 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select()
2979 SrcReg = X86::EDX; LoReg = HiReg = 0; in Select()
2982 SrcReg = X86::RDX; LoReg = HiReg = 0; in Select()
3054 assert(HiReg && "Register for high half is not defined!"); in Select()
3055 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT, in Select()
3096 unsigned LoReg, HiReg, ClrReg; in Select() local
3101 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
3105 LoReg = X86::AX; HiReg = X86::DX; in Select()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp363 unsigned HiReg = MRI.createVirtualRegister(RC); in selectG_CONSTANT() local
369 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg) in selectG_CONSTANT()
376 .addReg(HiReg) in selectG_CONSTANT()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
696 .addReg(HiReg); in expandBuildPairF64()
701 .addReg(HiReg); in expandBuildPairF64()
DMipsSEFrameLowering.cpp285 unsigned HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
301 std::swap(LoReg, HiReg); in expandBuildPairF64()
304 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp310 unsigned HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
326 std::swap(LoReg, HiReg); in expandBuildPairF64()
329 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
DMipsSEInstrInfo.cpp813 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
861 .addReg(HiReg); in expandBuildPairF64()
866 .addReg(HiReg); in expandBuildPairF64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp497 unsigned HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
511 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
530 unsigned HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
543 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) in emitBuildPairF64Pseudo()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp3965 unsigned HiReg, bool &containsReg) { in checkLowRegisterList() argument
3972 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp6102 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument
6110 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp6287 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument
6295 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp9054 unsigned HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
9056 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
9063 .addReg(HiReg).addReg(ReadAgainReg); in EmitInstrWithCustomInserter()

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