Home
last modified time | relevance | path

Searched refs:LoReg (Results 1 – 25 of 25) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td256 (LoReg (A2_vaddub (Zext64 $Rs), (Zext64 $Rt)))>;
261 (LoReg (A2_vsubub (Zext64 $Rs), (Zext64 $Rt)))>;
267 (LoReg (C2_vmux I1:$Pu, (Zext64 $Rs), (Zext64 $Rt)))>;
269 (LoReg (C2_vmux I1:$Pu, (Zext64 $Rs), (Zext64 $Rt)))>;
340 (LoReg (S2_packhl (HiReg $Rs), (LoReg $Rs)))>;
358 (A2_combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
362 (A2_combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
379 (LoReg (S2_vtrunewh (v2i32 (A2_combineii 0, 0)),
385 (vmpyh (LoReg $Rs), (LoReg $Rt)))>;
389 (vmpyh (LoReg (S2_vsxtbh $Rs)), (LoReg (S2_vsxtbh $Rt))))>;
[all …]
DHexagonCopyToCombine.cpp734 unsigned LoReg = LoOperand.getReg(); in emitCombineIR() local
745 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
753 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
760 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
768 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
775 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
833 unsigned LoReg = LoOperand.getReg(); in emitCombineRR() local
843 .addReg(LoReg, LoRegKillFlag); in emitCombineRR()
DHexagonInstrInfo.td30 def LoReg: OutPatFrag<(ops node:$Rs),
3197 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
3621 defm: Storexm_pat<truncstorei8, I64, s32_0ImmPred, LoReg, S2_storerb_io>;
3622 defm: Storexm_pat<truncstorei16, I64, s31_1ImmPred, LoReg, S2_storerh_io>;
3623 defm: Storexm_pat<truncstorei32, I64, s30_2ImmPred, LoReg, S2_storeri_io>;
3626 def: Storexm_simple_pat<truncstorei8, I64, LoReg, S2_storerb_io>;
3627 def: Storexm_simple_pat<truncstorei16, I64, LoReg, S2_storerh_io>;
3628 def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>;
4264 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
4899 (A2_sxtw (LoReg DoubleRegs:$src1))>;
[all …]
DHexagonFrameLowering.cpp827 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::subreg_loreg); in insertCFIInstructionsAt() local
829 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true); in insertCFIInstructionsAt()
DHexagonInstrInfoV5.td794 (LoReg (F2_conv_df2d_chop F64:$src1))>,
DHexagonIntrinsics.td766 (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>;
DHexagonInstrInfoV4.td3872 def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPatterns.td116 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
402 def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>;
403 def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>;
404 def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>;
423 def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>;
424 def: Pat<(i1 (trunc I64:$Rs)), (C2_tfrrp (LoReg $Rs))>;
444 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>;
446 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>;
456 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
459 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
[all …]
DHexagonCopyToCombine.cpp763 unsigned LoReg = LoOperand.getReg(); in emitCombineIR() local
774 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
782 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
789 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
797 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
804 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
862 unsigned LoReg = LoOperand.getReg(); in emitCombineRR() local
881 .addReg(LoReg, LoRegKillFlag); in emitCombineRR()
DHexagonIntrinsics.td744 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
746 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
788 (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>;
DHexagonFrameLowering.cpp947 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
949 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true); in insertCFIInstructionsAt()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsExpandPseudo.cpp89 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in ExpandBuildPairF64() local
97 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg); in ExpandBuildPairF64()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelDAGToDAG.cpp1838 unsigned LoReg; in Select() local
1841 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break; in Select()
1842 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; in Select()
1843 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; in Select()
1844 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; in Select()
1847 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select()
1884 unsigned LoReg, HiReg; in Select() local
1887 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; in Select()
1888 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; in Select()
1889 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; in Select()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2137 unsigned LoReg; in Select() local
2140 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break; in Select()
2141 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; in Select()
2142 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; in Select()
2143 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; in Select()
2146 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select()
2184 unsigned SrcReg, LoReg, HiReg; in Select() local
2189 SrcReg = LoReg = X86::AL; HiReg = X86::AH; in Select()
2193 SrcReg = LoReg = X86::AX; HiReg = X86::DX; in Select()
2197 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.cpp267 unsigned &LoReg, in splitReg() argument
271 LoReg = getSubReg(Reg, AVR::sub_lo); in splitReg()
DAVRRegisterInfo.h53 void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2923 unsigned LoReg, Opc; in Select() local
2927 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; in Select()
2928 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; in Select()
2929 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; in Select()
2932 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select()
2967 unsigned SrcReg, LoReg, HiReg; in Select() local
2972 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select()
2976 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select()
2979 SrcReg = X86::EDX; LoReg = HiReg = 0; in Select()
2982 SrcReg = X86::RDX; LoReg = HiReg = 0; in Select()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp362 unsigned LoReg = MRI.createVirtualRegister(RC); in selectG_CONSTANT() local
366 BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg) in selectG_CONSTANT()
374 .addReg(LoReg) in selectG_CONSTANT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp309 unsigned LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
326 std::swap(LoReg, HiReg); in expandBuildPairF64()
327 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
DMipsSEInstrInfo.cpp813 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
842 .addReg(LoReg); in expandBuildPairF64()
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp284 unsigned LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
301 std::swap(LoReg, HiReg); in expandBuildPairF64()
302 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
DMipsSEInstrInfo.cpp651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
680 .addReg(LoReg); in expandBuildPairF64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp496 unsigned LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local
507 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg) in emitSplitF64Pseudo()
529 unsigned LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
538 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())) in emitBuildPairF64Pseudo()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp9053 unsigned LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
9057 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); in EmitInstrWithCustomInserter()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp10385 unsigned LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
10389 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); in EmitInstrWithCustomInserter()