| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 332 MADD_S = 4, enumerator
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| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 365 MADD_S = 4, enumerator
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| /external/v8/src/mips/ |
| D | constants-mips.h | 715 MADD_S = ((4U << 3) + 0), enumerator
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| D | disasm-mips.cc | 1621 case MADD_S: in DecodeTypeRegister()
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| D | assembler-mips.cc | 2777 GenInstrRegister(COP1X, fr, ft, fs, fd, MADD_S); in madd_s()
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| D | simulator-mips.cc | 3736 case MADD_S: { in DecodeTypeRegisterCOP1X()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 746 MADD_S = ((4U << 3) + 0), enumerator
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| D | disasm-mips64.cc | 1408 case MADD_S: in DecodeTypeRegisterCOP1X()
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| D | simulator-mips64.cc | 3611 case MADD_S: { in DecodeTypeRegisterCOP1X()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 489 (instrs MADD_D32, MADD_D64, MADD_S, MSUB_D32, MSUB_D64, MSUB_S,
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| D | MipsInstrFPU.td | 619 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 481 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 925 {DBGFIELD("MADD_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #650
1945 {DBGFIELD("MADD_S") 1, false, false, 58, 2, 13, 1, 1, 1}, // #650
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| D | MipsGenAsmWriter.inc | 2985 268458784U, // MADD_S
5616 4672U, // MADD_S
7125 // MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MSUB_D32, MSUB_D32...
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| D | MipsGenMCCodeEmitter.inc | 1770 UINT64_C(1275068448), // MADD_S
3119 case Mips::MADD_S:
9496 …Mips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | Feature_HasMadd4 | 0, // MADD_S = 1757
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| D | MipsGenInstrInfo.inc | 1772 MADD_S = 1757,
3307 MADD_S = 650,
5817 …, 4, 1, 4, 650, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1757 = MADD_S
10173 { Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM },
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| D | MipsGenGlobalISel.inc | 13633 …f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32O…
13634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
13654 …{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32O…
13655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
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| D | MipsGenDAGISel.inc | 27602 /* 51872*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_S), 0,
27605 …// Dst: (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f…
27631 /* 51927*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_S), 0,
27634 …// Dst: (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f…
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| D | MipsGenDisassemblerTables.inc | 3665 /* 4526 */ MCD::OPC_Decode, 221, 13, 227, 1, // Opcode: MADD_S
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| D | MipsGenAsmMatcher.inc | 6549 …{ 5684 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32A…
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1024 33576995U, // MADD_S
2738 5U, // MADD_S
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| D | MipsGenDisassemblerTables.inc | 1221 /* 3388 */ MCD_OPC_Decode, 239, 7, 91, // Opcode: MADD_S
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