| /external/u-boot/arch/mips/lib/ |
| D | genex.S | 81 MFC0 v1, CP0_EPC
199 MFC0 k1, CP0_DEBUG
220 MFC0 k1, CP0_DESAVE
|
| /external/u-boot/arch/mips/cpu/ |
| D | cm_init.S | 27 1: MFC0 t0, CP0_CMGCRBASE
|
| /external/u-boot/arch/mips/include/asm/ |
| D | asm.h | 406 #define MFC0 mfc0 macro
410 #define MFC0 dmfc0 macro
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 599 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0) in emitInterruptPrologueStub()
613 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) in emitInterruptPrologueStub()
624 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) in emitInterruptPrologueStub()
|
| D | MipsScheduleP5600.td | 85 MFC0, MTC0)>;
|
| D | MipsInstrInfo.td | 2423 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd, II_MFC0>,
2719 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>,
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 574 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0) in emitInterruptPrologueStub()
588 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) in emitInterruptPrologueStub()
599 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) in emitInterruptPrologueStub()
|
| D | MipsInstrInfo.td | 2054 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd, II_MFC0>, MFC3OP_FM<0x10, 0>,
2256 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 683 {DBGFIELD("MFC0") 1, false, false, 19, 2, 2, 1, 0, 0}, // #408
1703 {DBGFIELD("MFC0") 1, false, false, 38, 3, 1, 1, 0, 0}, // #408
|
| D | MipsGenMCCodeEmitter.inc | 1808 UINT64_C(1073741824), // MFC0
5772 case Mips::MFC0:
9534 Feature_HasStdEnc | Feature_NotInMicroMips | 0, // MFC0 = 1795
|
| D | MipsGenAsmWriter.inc | 3023 268451842U, // MFC0
5654 2U, // MFC0
|
| D | MipsGenInstrInfo.inc | 1810 MFC0 = 1795,
3065 MFC0 = 408,
5855 …modeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1795 = MFC0
|
| D | MipsGenAsmMatcher.inc | 6603 …{ 6027 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc…
6605 …{ 6027 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature…
|
| D | MipsGenDisassemblerTables.inc | 3124 /* 1651 */ MCD::OPC_Decode, 131, 14, 190, 1, // Opcode: MFC0
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1054 1107312650U, // MFC0
2768 0U, // MFC0
|
| D | MipsGenDisassemblerTables.inc | 744 /* 1345 */ MCD_OPC_Decode, 141, 8, 58, // Opcode: MFC0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5196 case Mips::MFC0: in checkTargetMatchPredicate()
|