| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/ |
| D | MachineInstrTest.cpp | 124 auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc()); in TEST() local
125 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
126 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); in TEST()
130 ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs)); in TEST()
131 ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs)); in TEST()
133 ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs)); in TEST()
134 ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs)); in TEST()
158 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { in checkHashAndIsEqualMatch() argument
159 bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2); in checkHashAndIsEqualMatch()
160 bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1); in checkHashAndIsEqualMatch()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 193 MachineInstr *MI2 = nullptr,
392 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
397 if (!GetImm(MI2, 2, Offset2)) in ConsecutiveInstr()
401 unsigned Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
459 MachineInstr *MI2 = &*NextMII; in ReduceXWtoXWP() local
469 if (!CheckXWPInstr(MI2, ReduceToLwp, Entry)) in ReduceXWtoXWP()
473 unsigned Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP()
478 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
479 bool ConsecutiveBackward = ConsecutiveInstr(MI2, MI1); in ReduceXWtoXWP()
485 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward); in ReduceXWtoXWP()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 480 MachineInstr *MI2 = *I2; in hoistAndMergeSGPRInits() local
515 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
516 if (!intereferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
519 << printMBBReference(*MI2->getParent()) << " " << *MI2); in hoistAndMergeSGPRInits()
520 MI2->eraseFromParent(); in hoistAndMergeSGPRInits()
525 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
526 if (!intereferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
537 MI2->getParent()); in hoistAndMergeSGPRInits()
544 if (!intereferes(MI1, I) && !intereferes(MI2, I)) { in hoistAndMergeSGPRInits()
549 << printMBBReference(*MI2->getParent()) << " to " in hoistAndMergeSGPRInits()
[all …]
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| D | AMDGPUSubtarget.cpp | 641 MachineInstr &MI2 = *SU.getInstr(); in apply() local
642 if (!MI2.mayLoad() && !MI2.mayStore()) { in apply()
652 if ((TII->isVMEM(MI1) && TII->isVMEM(MI2)) || in apply()
653 (TII->isFLAT(MI1) && TII->isFLAT(MI2)) || in apply()
654 (TII->isSMRD(MI1) && TII->isSMRD(MI2)) || in apply()
655 (TII->isDS(MI1) && TII->isDS(MI2))) { in apply()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | DFAPacketizer.cpp | 361 const MachineInstr &MI2, in alias() argument
363 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
367 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias()
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| D | TargetInstrInfo.cpp | 679 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
683 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
686 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
694 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
699 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
701 std::swap(MI1, MI2); in hasReassociableSibling()
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| D | MachineInstr.cpp | 336 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) { in hasIdenticalMMOs() argument
338 auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end(); in hasIdenticalMMOs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 156 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply() local
157 if (!QII->isHVXVec(MI2)) in apply()
159 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) { in apply()
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| D | HexagonInstrInfo.h | 408 const MachineInstr &MI2) const;
420 const MachineInstr &MI2) const;
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| D | HexagonVLIWPacketizer.h | 134 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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| D | HexagonVLIWPacketizer.cpp | 961 MachineInstr &MI2) { in arePredicatesComplements() argument
965 getPredicateSense(MI2, HII) == PK_Unknown) in arePredicatesComplements()
1018 unsigned PReg2 = getPredicatedRegister(MI2, HII); in arePredicatesComplements()
1022 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1023 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
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| D | HexagonInstrInfo.cpp | 2561 const MachineInstr &MI2) const { in isToBeScheduledASAP()
2565 int N = MI2.getNumOperands(); in isToBeScheduledASAP()
2567 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg()) in isToBeScheduledASAP()
2570 if (mayBeNewStore(MI2)) in isToBeScheduledASAP()
2571 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi) in isToBeScheduledASAP()
2572 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2573 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
2878 const MachineInstr &MI2) const { in addLatencyToSchedule()
2879 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
2880 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 571 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
575 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
578 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
586 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
591 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
593 std::swap(MI1, MI2); in hasReassociableSibling()
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| D | MachineInstr.cpp | 905 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) { in hasIdenticalMMOs() argument
907 auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end(); in hasIdenticalMMOs()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 249 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
253 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 250 const MachineInstr &MI2, unsigned N2) const;
365 const MachineInstr &MI2, in getAddrDispShift() argument
368 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 269 const MachineInstr &MI2, unsigned N2) const;
392 const MachineInstr &MI2, in getAddrDispShift() argument
395 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
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| D | X86ISelLowering.h | 1305 MachineInstr &MI2,
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| /external/clang/test/Analysis/ |
| D | padding_cpp.cpp | 102 class MI2 : public PaddedA, public InnerPaddedB { // xxxexpected-warning{{Excessive padding in 'cla… class
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | DFAPacketizer.h | 212 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.h | 97 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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| D | HexagonVLIWPacketizer.cpp | 845 MachineInstr &MI2) { in arePredicatesComplements() argument
849 getPredicateSense(MI2, HII) == PK_Unknown) in arePredicatesComplements()
902 unsigned PReg2 = getPredicatedRegister(MI2, HII); in arePredicatesComplements()
906 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
907 HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2); in arePredicatesComplements()
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| D | HexagonInstrInfo.cpp | 2933 const MachineInstr *MI2) const { in addLatencyToSchedule()
2934 if (isV60VectorInstruction(MI1) && isV60VectorInstruction(MI2)) in addLatencyToSchedule()
2935 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 317 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
321 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 317 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
321 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
|