| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
166 static bool selectMergeValues(MachineInstrBuilder &MIB, in selectMergeValues() argument
175 unsigned VReg0 = MIB->getOperand(0).getReg(); in selectMergeValues()
180 unsigned VReg1 = MIB->getOperand(1).getReg(); in selectMergeValues()
185 unsigned VReg2 = MIB->getOperand(2).getReg(); in selectMergeValues()
191 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
192 MIB.add(predOps(ARMCC::AL)); in selectMergeValues()
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| D | ARMExpandPseudoInsts.cpp | 479 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
498 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
502 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
504 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
506 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
508 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
512 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
515 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
516 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
540 MIB.add(AM6Offset); in ExpandVLD()
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| D | ARMBaseInstrInfo.cpp | 773 MachineInstrBuilder MIB = in copyFromCPSR() local
779 MIB.addImm(0x800); in copyFromCPSR()
781 MIB.add(predOps(ARMCC::AL)) in copyFromCPSR()
793 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); in copyToCPSR() local
796 MIB.addImm(0x800); in copyToCPSR()
798 MIB.addImm(8); in copyToCPSR()
800 MIB.addReg(SrcReg, getKillRegState(KillSrc)) in copyToCPSR()
836 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg() local
837 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
839 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrBuilder.h | 91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
99 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
108 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
115 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
123 addFullAddress(const MachineInstrBuilder &MIB, in addFullAddress() argument
128 MIB.addReg(AM.Base.Reg); in addFullAddress()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 125 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
128 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
144 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
145 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
149 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { in addOffset() argument
150 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
158 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
160 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
165 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
168 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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| D | X86CallLowering.cpp | 104 MachineInstrBuilder &MIB, CCAssignFn *AssignFn) in OutgoingValueHandler()
105 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingValueHandler()
128 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
143 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg); in assignValueToReg() local
144 ExtReg = MIB->getOperand(0).getReg(); in assignValueToReg()
179 MachineInstrBuilder &MIB; member
192 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); in lowerReturn() local
210 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86); in lowerReturn()
215 MIRBuilder.insertInstr(MIB); in lowerReturn()
303 CCAssignFn *AssignFn, MachineInstrBuilder &MIB) in CallReturnHandler()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrBuilder.h | 59 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
62 return MIB.addReg(Reg).addImm(0).addReg(0); in addDirectMem()
66 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
67 return MIB.addImm(Offset).addReg(0); in addOffset()
75 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
83 addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0) in addRegReg()
90 addFullAddress(const MachineInstrBuilder &MIB, const SystemZAddressMode &AM) { in addFullAddress() argument
92 MIB.addReg(AM.Base.Reg); in addFullAddress()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 119 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
122 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
127 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
128 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
136 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
138 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
143 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
151 addFullAddress(const MachineInstrBuilder &MIB, in addFullAddress() argument
156 MIB.addReg(AM.Base.Reg); in addFullAddress()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 401 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
409 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
411 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
413 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
415 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
422 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
425 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
435 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
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| D | ARMBaseInstrInfo.cpp | 685 MachineInstrBuilder MIB = in copyFromCPSR() local
691 MIB.addImm(0x800); in copyFromCPSR()
693 AddDefaultPred(MIB); in copyFromCPSR()
695 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
706 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); in copyToCPSR() local
709 MIB.addImm(0x800); in copyToCPSR()
711 MIB.addImm(8); in copyToCPSR()
713 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyToCPSR()
715 AddDefaultPred(MIB); in copyToCPSR()
717 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
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| D | Thumb2SizeReduction.cpp | 450 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1)) in ReduceLoadStore() local
458 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in ReduceLoadStore()
461 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore()
553 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore() local
558 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead); in ReduceLoadStore()
561 MIB.addOperand(MI->getOperand(0)); in ReduceLoadStore()
562 MIB.addOperand(MI->getOperand(1)); in ReduceLoadStore()
565 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
570 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
576 MIB.addOperand(MI->getOperand(OpNum)); in ReduceLoadStore()
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| D | ThumbRegisterInfo.cpp | 164 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg() local
166 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmInReg()
168 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
170 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
171 AddDefaultPred(MIB); in emitThumbRegPlusImmInReg()
304 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg); in emitThumbRegPlusImmediate() local
306 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmediate()
307 MIB.addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmediate()
309 MIB.addImm(CopyImm); in emitThumbRegPlusImmediate()
311 AddDefaultPred(MIB.setMIFlags(MIFlags)); in emitThumbRegPlusImmediate()
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| D | ARMInstrInfo.cpp | 122 MachineInstrBuilder MIB; in expandLoadStackGuard() local
124 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg) in expandLoadStackGuard()
129 MIB.addMemOperand(MMO); in expandLoadStackGuard()
130 MIB = BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg); in expandLoadStackGuard()
131 MIB.addReg(Reg, RegState::Kill).addImm(0); in expandLoadStackGuard()
132 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandLoadStackGuard()
133 AddDefaultPred(MIB); in expandLoadStackGuard()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 208 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
241 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
254 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
266 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
312 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
324 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
358 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
360 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
361 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
368 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 209 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
241 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
254 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
266 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
312 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
324 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
366 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
368 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
369 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
376 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 313 MachineInstrBuilder MIB; in changeLoad() local
319 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
320 MIB.addOperand(OldMI->getOperand(0)); in changeLoad()
321 MIB.addOperand(OldMI->getOperand(2)); in changeLoad()
322 MIB.addOperand(OldMI->getOperand(3)); in changeLoad()
323 MIB.addOperand(ImmOp); in changeLoad()
329 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) in changeLoad()
334 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
341 DEBUG(dbgs() << "[TO]: " << MIB << "\n"); in changeLoad()
345 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 417 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
425 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandVLD()
428 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
430 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
433 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
436 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
437 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
440 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
450 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
451 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
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| D | Thumb1RegisterInfo.cpp | 129 MachineInstrBuilder MIB = in emitThumbRegPlusImmInReg() local
132 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmInReg()
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
137 AddDefaultPred(MIB); in emitThumbRegPlusImmInReg()
241 const MachineInstrBuilder MIB = in emitThumbRegPlusImmediate() local
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); in emitThumbRegPlusImmediate()
260 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmediate() local
262 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmediate()
263 MIB.addReg(DestReg).addImm(ThisVal); in emitThumbRegPlusImmediate()
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| D | Thumb2SizeReduction.cpp | 445 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc)); in ReduceLoadStore() local
447 MIB.addOperand(MI->getOperand(0)); in ReduceLoadStore()
448 MIB.addOperand(MI->getOperand(1)); in ReduceLoadStore()
451 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
456 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); in ReduceLoadStore()
461 MIB.addOperand(MI->getOperand(OpNum)); in ReduceLoadStore()
464 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in ReduceLoadStore()
467 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore()
469 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); in ReduceLoadStore()
505 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), in ReduceSpecial() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 115 MachineInstrBuilder MIB, CCAssignFn *AssignFn) in CallReturnHandler()
116 : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} in CallReturnHandler()
119 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
122 MachineInstrBuilder MIB; member
127 MachineInstrBuilder MIB, CCAssignFn *AssignFn, in OutgoingArgHandler()
129 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingArgHandler()
151 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
183 MachineInstrBuilder MIB; member
234 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR); in lowerReturn() local
257 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn); in lowerReturn()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 492 MachineInstrBuilder MIB; in changeLoad() local
498 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
499 MIB.add(OldMI->getOperand(0)); in changeLoad()
500 MIB.add(OldMI->getOperand(2)); in changeLoad()
501 MIB.add(OldMI->getOperand(3)); in changeLoad()
502 MIB.add(ImmOp); in changeLoad()
508 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) in changeLoad()
513 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
520 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); in changeLoad()
524 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUInstrInfo.cpp | 360 MachineInstrBuilder MIB; in InsertBranch() local
368 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel); in InsertBranch()
374 MIB = BuildMI(&MBB, DL, get(SPU::BR)); in InsertBranch()
375 MIB.addMBB(TBB); in InsertBranch()
378 DEBUG((*MIB).dump()); in InsertBranch()
382 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA)); in InsertBranch()
383 MIB.addSym(branchLabel); in InsertBranch()
384 MIB.addMBB(TBB); in InsertBranch()
388 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); in InsertBranch()
389 MIB.addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 102 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr() local
106 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
108 MIB.addImm(Cond[i].getImm()); in BuildCondBr()
112 MIB.addMBB(TBB); in BuildCondBr()
399 MachineInstrBuilder MIB; in genInstrWithNewOpc() local
430 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
440 MIB->RemoveOperand(0); in genInstrWithNewOpc()
443 MIB.addOperand(I->getOperand(J)); in genInstrWithNewOpc()
446 MIB.addImm(0); in genInstrWithNewOpc()
451 MIB.addOperand(I->getOperand(0)); in genInstrWithNewOpc()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 75 MachineInstrBuilder &MIB) in CallReturnHandler() argument
76 : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
80 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
83 MachineInstrBuilder &MIB; member in __anonfc1868240111::CallReturnHandler
127 MachineInstrBuilder &MIB) in OutgoingValueHandler() argument
128 : MipsHandler(MIRBuilder, MRI), MIB(MIB) {} in OutgoingValueHandler()
142 MachineInstrBuilder &MIB; member in __anonfc1868240211::OutgoingValueHandler
149 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
327 MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Mips::JAL); in lowerCall() local
328 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
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| D | MicroMipsSizeReduction.cpp | 622 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); in ReplaceInstruction() local
625 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
628 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
629 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
634 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
635 MIB.add(MI->getOperand(1)); in ReplaceInstruction()
636 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
638 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
639 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
640 MIB.add(MI->getOperand(1)); in ReplaceInstruction()
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