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Searched refs:MRM0r (Results 1 – 25 of 37) sorted by relevance

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/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
137 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) || in needsModRMForDecode()
153 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)) in isRegFormat()
727 case X86Local::MRM0r: in emitInstructionSpecifier()
819 case X86Local::MRM0r: in emitDecodePath()
827 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); in emitDecodePath()
908 case X86Local::MRM0r: in emitDecodePath()
916 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); in emitDecodePath()
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h215 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
490 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp578 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix()
964 case X86II::MRM0r: case X86II::MRM1r: in EncodeInstruction()
972 (TSFlags & X86II::FormMask)-X86II::MRM0r, in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td417 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
420 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
423 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
426 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
431 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
434 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
438 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
441 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
447 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
450 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrSystem.td346 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
350 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
355 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
451 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
453 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
DX86InstrArithmetic.td383 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
396 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
404 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
408 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1093 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1130 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1131 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1132 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1133 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
DX86InstrCMovSetCC.td79 def r : I<opc, MRM0r, (outs GR8:$dst), (ins),
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)); in isRegFormat()
715 case X86Local::MRM0r: in emitInstructionSpecifier()
852 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
856 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); in emitDecodePath()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td458 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
461 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
464 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
467 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
472 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
475 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
478 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
481 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
487 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
490 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td271 def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">;
272 def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">;
273 def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">;
401 def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op),
409 def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op),
545 def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op">;
645 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), "ffree\t$reg">;
646 def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg), "ffreep\t$reg">;
DX86InstrSystem.td373 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
378 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
383 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
608 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
611 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
DX86InstrArithmetic.td429 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
433 def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
436 def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
439 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
1162 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1202 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1203 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1204 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1206 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td471 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
474 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
477 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
480 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
485 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
488 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
492 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
496 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
503 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
507 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td268 def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">;
269 def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">;
270 def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">;
383 def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op),
391 def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op),
539 def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>;
632 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg),
DX86InstrSystem.td404 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
408 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
413 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
573 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
576 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
DX86InstrArithmetic.td455 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
460 def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
464 def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
468 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
1197 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1237 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1238 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1239 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1240 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h295 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
685 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp869 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix()
1020 case X86II::MRM0r: case X86II::MRM1r: in DetermineREXPrefix()
1355 case X86II::MRM0r: case X86II::MRM1r: in encodeInstruction()
1365 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r, in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h343 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3 enumerator
727 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp942 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix()
1092 case X86II::MRM0r: case X86II::MRM1r: in DetermineREXPrefix()
1486 case X86II::MRM0r: case X86II::MRM1r: in encodeInstruction()
1496 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r, in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86RecognizableInstr.h117 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, enumerator
DX86RecognizableInstr.cpp625 case X86Local::MRM0r: in emitInstructionSpecifier()
743 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
747 filter = llvm::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); in emitDecodePath()
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DTargetInstrInfo.td52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
/external/llvm/test/TableGen/
DTargetInstrInfo.td52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;

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