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Searched refs:MRM3r (Results 1 – 25 of 38) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h215 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
491 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp579 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix()
965 case X86II::MRM2r: case X86II::MRM3r: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td326 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
328 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
331 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
334 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
336 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
339 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
342 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
344 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
347 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
350 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
[all …]
DX86InstrSystem.td226 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
463 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$dst),
465 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$dst),
DX86InstrArithmetic.td312 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
316 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
320 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
324 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
1102 defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td361 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
363 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
365 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
367 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
372 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
374 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
376 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
378 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
380 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
382 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
[all …]
DX86InstrFPStack.td283 def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
407 def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op),
415 def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op),
547 def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op">;
DX86InstrSystem.td250 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
626 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
629 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
DX86InstrArithmetic.td352 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
356 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
360 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
364 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
1172 defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td377 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
379 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
382 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
385 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
387 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
390 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
393 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
395 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
398 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
401 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
[all …]
DX86InstrFPStack.td293 def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
389 def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op),
397 def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op),
541 def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>;
DX86InstrSystem.td254 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
591 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
594 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
DX86InstrArithmetic.td377 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
381 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
385 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
389 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
1207 defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
730 case X86Local::MRM3r: in emitInstructionSpecifier()
822 case X86Local::MRM3r: in emitDecodePath()
911 case X86Local::MRM3r: in emitDecodePath()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h295 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
686 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp870 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix()
1021 case X86II::MRM2r: case X86II::MRM3r: in DetermineREXPrefix()
1356 case X86II::MRM2r: case X86II::MRM3r: in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h343 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3 enumerator
728 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp943 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix()
1093 case X86II::MRM2r: case X86II::MRM3r: in DetermineREXPrefix()
1487 case X86II::MRM2r: case X86II::MRM3r: in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86RecognizableInstr.h117 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, enumerator
DX86RecognizableInstr.cpp628 case X86Local::MRM3r: in emitInstructionSpecifier()
744 case X86Local::MRM2r: case X86Local::MRM3r: in emitDecodePath()
DX86FoldTablesEmitter.cpp418 (MemFormNum == X86Local::MRM3m && RegFormNum == X86Local::MRM3r) || in areOppositeForms()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
718 case X86Local::MRM3r: in emitInstructionSpecifier()
853 case X86Local::MRM2r: case X86Local::MRM3r: in emitDecodePath()
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
/external/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;

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