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Searched refs:MRMSrcReg (Results 1 – 25 of 58) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrExtension.td41 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
45 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
51 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
58 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
62 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
68 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
78 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
92 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
98 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
104 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
[all …]
DX86InstrMMX.td28 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
44 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
63 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
78 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
93 def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
107 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
116 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
135 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
164 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
176 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
[all …]
DX86InstrSSE.td26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
325 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
658 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
882 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
884 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
886 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
[all …]
DX86Instr3DNow.td37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
57 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
DX86InstrSystem.td120 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
122 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
133 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
135 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
167 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
169 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
171 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
188 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
194 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
199 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
[all …]
DX86InstrCMovSetCC.td21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
26 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
31 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
DX86InstrFMA.td19 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
27 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
DX86InstrVMX.td50 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
54 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrExtension.td41 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
49 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
57 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
67 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
75 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
83 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
96 def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
99 def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
116 def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg,
126 def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg,
[all …]
DX86InstrMMX.td38 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
57 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
79 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
97 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
115 def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
131 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
142 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
164 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
196 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
213 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
[all …]
DX86InstrXOP.td15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
46 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
57 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
68 def Yrr : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
119 def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
143 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
172 def rr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
249 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
267 def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
299 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrSSE.td26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
48 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
71 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
94 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
178 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
374 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
792 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
799 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
808 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
815 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrMPX.td38 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
41 def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
49 def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
DX86InstrFMA.td40 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
61 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
81 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
181 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
202 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
222 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
271 def r_Int : FMA3S_Int<opc, MRMSrcReg, (outs RC:$dst),
420 def rr_REV : FMA4S<opc, MRMSrcReg, (outs RC:$dst),
454 def rr_Int_REV : FMA4S_Int<opc, MRMSrcReg, (outs VR128:$dst),
522 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrCMovSetCC.td22 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
28 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
34 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
/external/llvm/lib/Target/X86/
DX86InstrExtension.td43 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
51 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
59 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
69 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
77 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
85 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
98 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
108 def MOVSX32_NOREXrr8 : I<0xBE, MRMSrcReg,
123 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
131 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
[all …]
DX86InstrXOP.td15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
54 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
64 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
88 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
127 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
149 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
182 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
200 def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
227 def rrr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrMMX.td98 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
116 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
138 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
155 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
172 def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
188 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
199 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
221 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
253 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
273 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
[all …]
DX86Instr3DNow.td37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
57 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
DX86InstrMPX.td34 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
37 def 64rr: RI<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
45 def BNDMOVRMrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
DX86InstrFMA.td43 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
59 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
147 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
179 def r_Int : FMA3<opc, MRMSrcReg, (outs RC:$dst),
271 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
291 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
302 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
327 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
347 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
368 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrSSE.td246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
515 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
777 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1352 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1359 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1368 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1374 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrAVX512.td437 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
551 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
802 def r_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
808 def rk_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
817 def rkz_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
831 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
887 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
1053 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1078 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1157 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
[all …]
DX86InstrSystem.td127 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
130 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
146 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
149 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
184 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
186 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
188 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
208 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
216 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
222 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
[all …]
DX86InstrCMovSetCC.td21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),

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