| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 307 MSUB = 4, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 807 // MADD*/MSUB*
810 def MSUB : MArithR<4, "msub", MipsMSub>;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 661 TmpInst.setOpcode(Mips::MSUB);
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| D | MipsGenMCCodeEmitter.inc | 1926 UINT64_C(1879048196), // MSUB
5184 case Mips::MSUB:
9652 …_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MSUB = 1913
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| D | MipsGenAsmWriter.inc | 3141 18346U, // MSUB
5772 0U, // MSUB
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| D | MipsGenInstrInfo.inc | 1928 MSUB = 1913,
5973 …Effects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1913 = MSUB
10192 { Mips::MSUB, Mips::MSUB, Mips::MSUB_MM },
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 188 def : InstRW<[P5600WriteAL2MAdd], (instrs MADD, MADDU, MSUB, MSUBU,
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| D | MipsInstrInfo.td | 2375 // MADD*/MSUB*
2380 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
2398 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 189 // MUL/MNEG are aliases for MADD/MSUB.
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| D | AArch64InstrInfo.td | 719 defm MSUB : MulAccum<1, "msub", sub>;
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| D | AArch64InstrFormats.td | 1449 // MADD/MSUB generation is decided by MachineCombiner.cpp
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 191 // MUL/MNEG are aliases for MADD/MSUB.
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| D | AArch64InstrInfo.td | 918 defm MSUB : MulAccum<1, "msub", sub>;
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| D | AArch64InstrFormats.td | 1807 // MADD/MSUB generation is decided by MachineCombiner.cpp
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 2008 // MADD*/MSUB*
2013 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
2030 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1083 MSUB = MSUB_w, enumerator
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| D | assembler-arm64.cc | 1469 DataProcessing3Source(rd, rn, rm, zr, MSUB); in mneg()
1478 DataProcessing3Source(rd, rn, rm, ra, MSUB); in msub()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 476 (instregex "F(N)?MSUB(S)?o$"),
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1256 MSUB = MSUB_w, enumerator
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| D | assembler-aarch64.cc | 897 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MSUB); in mneg()
905 DataProcessing3Source(rd, rn, rm, ra, MSUB); in msub()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1150 17949U, // MSUB
2864 0U, // MSUB
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| D | MipsGenDisassemblerTables.inc | 1290 /* 3669 */ MCD_OPC_Decode, 237, 8, 24, // Opcode: MSUB
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| /external/owasp/sanitizer/lib/htmlparser-1.3/ |
| D | htmlparser-1.3-with-transitions.jar | META-INF/MANIFEST.MF
nu/validator/htmlparser/tools/XSLT4HTML5XOM.class
XSLT4HTML5XOM ... |
| D | htmlparser-1.3.jar | META-INF/MANIFEST.MF
nu/validator/htmlparser/tools/XSLT4HTML5XOM.class
XSLT4HTML5XOM ... |
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 822 ### MSUB ### subsection
|