Searched refs:MSUBF_D (Results 1 – 17 of 17) sorted by relevance
| /external/v8/src/mips/ |
| D | constants-mips.h | 646 MSUBF_D = ((3U << 3) + 1), enumerator
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| D | disasm-mips.cc | 1183 case MSUBF_D: in DecodeTypeRegisterDRsType()
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| D | assembler-mips.cc | 2815 GenInstrRegister(COP1, D, ft, fs, fd, MSUBF_D); in msubf_d()
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| D | simulator-mips.cc | 2788 case MSUBF_D: in DecodeTypeRegisterDRsType()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 676 MSUBF_D = ((3U << 3) + 1), enumerator
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| D | disasm-mips64.cc | 1256 case MSUBF_D: in DecodeTypeRegisterDRsType()
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| D | assembler-mips64.cc | 3211 GenInstrRegister(COP1, D, ft, fs, fd, MSUBF_D); in msubf_d()
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| D | simulator-mips64.cc | 3106 case MSUBF_D: in DecodeTypeRegisterDRsType()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips32r6InstrInfo.td | 822 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips32r6InstrInfo.td | 936 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1151 2183153795U, // MSUBF_D
2865 0U, // MSUBF_D
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| D | MipsGenDisassemblerTables.inc | 3834 /* 823 */ MCD_OPC_Decode, 238, 8, 211, 1, // Opcode: MSUBF_D
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1927 UINT64_C(1176502297), // MSUBF_D
3653 case Mips::MSUBF_D:
9653 …dEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MSUBF_D = 1914
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| D | MipsGenAsmWriter.inc | 3142 285231697U, // MSUBF_D
5773 24U, // MSUBF_D
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| D | MipsGenInstrInfo.inc | 1929 MSUBF_D = 1914,
5974 …eledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1914 = MSUBF_D
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| D | MipsGenDisassemblerTables.inc | 6392 /* 1007 */ MCD::OPC_Decode, 250, 14, 214, 2, // Opcode: MSUBF_D
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| D | MipsGenAsmMatcher.inc | 6753 …{ 6578 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmRe…
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