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Searched refs:Op1 (Results 1 – 25 of 351) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenFastISel.inc1443 unsigned FastEmit_ISD_ADD_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1…
1446 return FastEmitInst_rr(X86::ADD8rr, X86::GR8RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
1449 unsigned FastEmit_ISD_ADD_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
1452 return FastEmitInst_rr(X86::ADD16rr, X86::GR16RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
1455 unsigned FastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
1458 return FastEmitInst_rr(X86::ADD32rr, X86::GR32RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
1461 unsigned FastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
1464 return FastEmitInst_rr(X86::ADD64rr, X86::GR64RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
1467 unsigned FastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool …
1471 return FastEmitInst_rr(X86::VPADDBrr, X86::VR128RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
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/external/capstone/arch/XCore/
DXCoreDisassembler.c192 static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) in Decode2OpInstruction() argument
209 *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2); in Decode2OpInstruction()
216 unsigned *Op1, unsigned *Op2, unsigned *Op3) in Decode3OpInstruction() argument
226 *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2); in Decode3OpInstruction()
309 unsigned Op1, Op2; in Decode2RInstruction() local
310 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RInstruction()
314 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); in Decode2RInstruction()
323 unsigned Op1, Op2; in Decode2RImmInstruction() local
324 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); in Decode2RImmInstruction()
328 MCOperand_CreateImm0(Inst, Op1); in Decode2RImmInstruction()
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/external/swiftshader/third_party/LLVM/lib/Analysis/
DInstructionSimplify.cpp129 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)) in ExpandBinOp() local
130 if (Op1->getOpcode() == OpcodeToExpand) { in ExpandBinOp()
132 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1); in ExpandBinOp()
168 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); in FactorizeBinOp() local
171 !Op1 || Op1->getOpcode() != OpcodeToExtract) in FactorizeBinOp()
176 Value *C = Op1->getOperand(0), *D = Op1->getOperand(1); in FactorizeBinOp()
241 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); in SimplifyAssociativeBinOp() local
263 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
265 Value *B = Op1->getOperand(0); in SimplifyAssociativeBinOp()
266 Value *C = Op1->getOperand(1); in SimplifyAssociativeBinOp()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenFastISel.inc1221 unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
1225 … return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1228 …return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKil…
1231 return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1234 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1239 unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
1243 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1248 unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool O…
1252 return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1257 unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool …
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineMulDivRem.cpp143 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local
144 if (match(Op1, m_AllOnes())) { in visitMul()
190 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) { in visitMul()
219 if (isa<Constant>(Op1)) { in visitMul()
224 Value *Mul = Builder.CreateMul(C1, Op1); in visitMul()
228 return BinaryOperator::CreateAdd(Builder.CreateMul(X, Op1), Mul); in visitMul()
235 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Constant(Op1C))) in visitMul()
239 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Neg(m_Value(Y)))) { in visitMul()
243 cast<OverflowingBinaryOperator>(Op1)->hasNoSignedWrap()) in visitMul()
251 Value *Y = Op1; in visitMul()
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DInstCombineShifts.cpp25 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms() local
26 assert(Op0->getType() == Op1->getType()); in commonShiftTransforms()
34 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) in commonShiftTransforms()
38 if (Constant *CUI = dyn_cast<Constant>(Op1)) in commonShiftTransforms()
46 if (match(Op0, m_Constant()) && match(Op1, m_Add(m_Value(A), m_Constant(C)))) in commonShiftTransforms()
56 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) { in commonShiftTransforms()
60 Op1->getName()); in commonShiftTransforms()
347 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, in FoldShiftByConstant() argument
352 if (!match(Op1, m_APInt(Op1C))) in FoldShiftByConstant()
390 ConstantExpr::getZExt(cast<Constant>(Op1), TrOp->getType()); in FoldShiftByConstant()
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DInstCombineAddSub.cpp921 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldAddWithConstant() local
923 if (!match(Op1, m_Constant(Op1C))) in foldAddWithConstant()
933 match(Op1, m_AllOnes())) in foldAddWithConstant()
939 return SelectInst::Create(X, AddOne(Op1C), Op1); in foldAddWithConstant()
946 if (!match(Op1, m_APInt(C))) in foldAddWithConstant()
953 return BinaryOperator::CreateOr(Op0, Op1); in foldAddWithConstant()
957 return BinaryOperator::CreateXor(Op0, Op1); in foldAddWithConstant()
1588 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitSub() local
1589 if (Value *V = dyn_castNegVal(Op1)) { in visitSub()
1592 if (const auto *BO = dyn_cast<BinaryOperator>(Op1)) { in visitSub()
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DInstCombineAndOrXor.cpp918 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); in foldAndOfICmps() local
921 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder); in foldAndOfICmps()
1219 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldCastedBitwiseLogic() local
1234 CastInst *Cast1 = dyn_cast<CastInst>(Op1); in foldCastedBitwiseLogic()
1285 Value *Op1 = I.getOperand(1); in foldAndToXor() local
1299 if (Op0->hasOneUse() || Op1->hasOneUse()) in foldAndToXor()
1311 Value *Op1 = I.getOperand(1); in foldOrToXor() local
1317 if (Op0->hasOneUse() || Op1->hasOneUse()) in foldOrToXor()
1319 match(Op1, m_Not(m_c_Or(m_Specific(A), m_Specific(B))))) in foldOrToXor()
1327 match(Op1, m_c_And(m_Not(m_Specific(A)), m_Specific(B)))) in foldOrToXor()
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/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/
DInstCombineMulDivRem.cpp101 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local
103 if (Value *V = SimplifyMulInst(Op0, Op1, TD)) in visitMul()
109 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X in visitMul()
112 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) { in visitMul()
164 if (isa<Constant>(Op1)) { in visitMul()
176 if (Value *Op1v = dyn_castNegVal(Op1)) in visitMul()
182 Value *Op1C = Op1; in visitMul()
188 BO = dyn_cast<BinaryOperator>(Op1); in visitMul()
220 return BinaryOperator::CreateAnd(Op0, Op1); in visitMul()
227 return BinaryOperator::CreateShl(Op1, Y); in visitMul()
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DInstCombineAddSub.cpp530 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitSub() local
532 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(), in visitSub()
541 if (Value *V = dyn_castNegVal(Op1)) { in visitSub()
549 return BinaryOperator::CreateXor(Op0, Op1); in visitSub()
553 return BinaryOperator::CreateNot(Op1); in visitSub()
558 if (match(Op1, m_Not(m_Value(X)))) in visitSub()
565 if (match(Op1, m_LShr(m_Value(X), m_ConstantInt(CI))) && in visitSub()
570 if (match(Op1, m_AShr(m_Value(X), m_ConstantInt(CI))) && in visitSub()
577 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) in visitSub()
582 if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1)) in visitSub()
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DInstCombineShifts.cpp24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms() local
32 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) in commonShiftTransforms()
36 if (ConstantInt *CUI = dyn_cast<ConstantInt>(Op1)) in commonShiftTransforms()
44 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) { in commonShiftTransforms()
48 Op1->getName()); in commonShiftTransforms()
311 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1, in FoldShiftByConstant() argument
319 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) { in FoldShiftByConstant()
324 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this)); in FoldShiftByConstant()
335 if (Op1->uge(TypeBits)) { in FoldShiftByConstant()
348 ConstantExpr::getShl(BOOp, Op1)); in FoldShiftByConstant()
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DInstCombineCompares.cpp1776 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitICmpInst() local
1781 if (getComplexity(Op0) < getComplexity(Op1)) { in visitICmpInst()
1783 std::swap(Op0, Op1); in visitICmpInst()
1787 if (Value *V = SimplifyICmpInst(I.getPredicate(), Op0, Op1, TD)) in visitICmpInst()
1797 Value *Xor = Builder->CreateXor(Op0, Op1, I.getName()+"tmp"); in visitICmpInst()
1801 return BinaryOperator::CreateXor(Op0, Op1); in visitICmpInst()
1804 std::swap(Op0, Op1); // Change icmp ugt -> icmp ult in visitICmpInst()
1808 return BinaryOperator::CreateAnd(Not, Op1); in visitICmpInst()
1811 std::swap(Op0, Op1); // Change icmp sgt -> icmp slt in visitICmpInst()
1814 Value *Not = Builder->CreateNot(Op1, I.getName()+"tmp"); in visitICmpInst()
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/external/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode2OpInstruction()
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
268 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); in Decode3OpInstruction()
347 unsigned Op1, Op2; in Decode2RInstruction() local
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
352 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); in Decode2RInstruction()
360 unsigned Op1, Op2; in Decode2RImmInstruction() local
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
365 Inst.addOperand(MCOperand::createImm(Op1)); in Decode2RImmInstruction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode2OpInstruction()
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
268 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); in Decode3OpInstruction()
347 unsigned Op1, Op2; in Decode2RInstruction() local
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
352 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); in Decode2RInstruction()
360 unsigned Op1, Op2; in Decode2RImmInstruction() local
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
365 Inst.addOperand(MCOperand::createImm(Op1)); in Decode2RImmInstruction()
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/external/tensorflow/tensorflow/core/api_def/
Dupdate_api_def_test.cc28 REGISTER_OP("Op1") in TEST()
36 REGISTER_OP("Op1") in TEST()
42 Summary for Op1. in TEST()
45 for Op1. in TEST()
54 name: "Op1" in TEST()
67 summary: "Summary for Op1." in TEST()
68 description: "Description\nfor Op1." in TEST()
79 REGISTER_OP("Op1") in TEST()
93 REGISTER_OP("Op1") in TEST()
96 Summary for Op1. in TEST()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc5567 unsigned fastEmit_ISD_ADD_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1…
5570 return fastEmitInst_rr(X86::ADD8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
5573 unsigned fastEmit_ISD_ADD_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
5576 return fastEmitInst_rr(X86::ADD16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
5579 unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
5582 return fastEmitInst_rr(X86::ADD32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
5585 unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
5588 return fastEmitInst_rr(X86::ADD64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
5591 unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool …
5595 return fastEmitInst_rr(X86::VPADDBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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/external/llvm/lib/Transforms/InstCombine/
DInstCombineMulDivRem.cpp177 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local
182 if (Value *V = SimplifyMulInst(Op0, Op1, DL, TLI, DT, AC)) in visitMul()
189 if (match(Op1, m_AllOnes())) { in visitMul()
243 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) { in visitMul()
269 if (isa<Constant>(Op1)) { in visitMul()
284 Value *Mul = Builder->CreateMul(C1, Op1); in visitMul()
288 return BinaryOperator::CreateAdd(Builder->CreateMul(X, Op1), Mul); in visitMul()
294 if (Value *Op1v = dyn_castNegVal(Op1)) { in visitMul()
298 match(Op1, m_NSWSub(m_Value(), m_Value()))) in visitMul()
307 Value *Op1C = Op1; in visitMul()
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DInstCombineAndOrXor.cpp878 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); in FoldAndOfICmps() local
881 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder); in FoldAndOfICmps()
1163 Value *Op1 = I.getOperand(1); in matchDeMorgansLaws() local
1166 if (Value *Op1NotVal = dyn_castNotVal(Op1)) in matchDeMorgansLaws()
1167 if (Op0->hasOneUse() && Op1->hasOneUse()) { in matchDeMorgansLaws()
1180 match(Op1, m_OneUse(m_Xor(m_ZExt(m_Value(B)), m_Specific(C1))))) { in matchDeMorgansLaws()
1202 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldCastedBitwiseLogic() local
1221 if ((match(Op0, m_BitCast(m_Value(BC))) && match(Op1, m_Constant(C)))) { in foldCastedBitwiseLogic()
1227 CastInst *Cast1 = dyn_cast<CastInst>(Op1); in foldCastedBitwiseLogic()
1283 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldBoolSextMaskToSelect() local
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenFastISel.inc4008 unsigned fastEmit_AArch64ISD_CMEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1…
4012 …return fastEmitInst_rr(AArch64::CMEQv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4017 …rch64ISD_CMEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4021 …return fastEmitInst_rr(AArch64::CMEQv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKil…
4026 …rch64ISD_CMEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4030 …return fastEmitInst_rr(AArch64::CMEQv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill…
4035 …rch64ISD_CMEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4039 …return fastEmitInst_rr(AArch64::CMEQv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKil…
4044 …rch64ISD_CMEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4048 …return fastEmitInst_rr(AArch64::CMEQv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/
DInstructionSimplify.cpp198 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)) in ExpandBinOp() local
199 if (Op1->getOpcode() == OpcodeToExpand) { in ExpandBinOp()
201 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1); in ExpandBinOp()
236 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); in SimplifyAssociativeBinOp() local
258 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
260 Value *B = Op1->getOperand(0); in SimplifyAssociativeBinOp()
261 Value *C = Op1->getOperand(1); in SimplifyAssociativeBinOp()
300 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
302 Value *B = Op1->getOperand(0); in SimplifyAssociativeBinOp()
303 Value *C = Op1->getOperand(1); in SimplifyAssociativeBinOp()
[all …]
/external/llvm/lib/Analysis/
DInstructionSimplify.cpp172 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)) in ExpandBinOp() local
173 if (Op1->getOpcode() == OpcodeToExpand) { in ExpandBinOp()
175 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1); in ExpandBinOp()
209 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); in SimplifyAssociativeBinOp() local
231 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
233 Value *B = Op1->getOperand(0); in SimplifyAssociativeBinOp()
234 Value *C = Op1->getOperand(1); in SimplifyAssociativeBinOp()
273 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
275 Value *B = Op1->getOperand(0); in SimplifyAssociativeBinOp()
276 Value *C = Op1->getOperand(1); in SimplifyAssociativeBinOp()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenFastISel.inc2625 unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool…
2629 return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2632 return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2635 return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2640 unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool…
2642 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2649 unsigned fastEmit_ARMISD_CMPZ_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, boo…
2653 return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2656 return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2659 return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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/external/swiftshader/third_party/subzero/pnacl-llvm/include/llvm/Bitcode/NaCl/
DNaClBitCodes.h224 static inline bool operator<(const NaClBitCodeAbbrevOp &Op1,
226 return Op1.Compare(Op2) < 0;
229 static inline bool operator<=(const NaClBitCodeAbbrevOp &Op1,
231 return Op1.Compare(Op2) <= 0;
234 static inline bool operator==(const NaClBitCodeAbbrevOp &Op1,
236 return Op1.Compare(Op2) == 0;
239 static inline bool operator!=(const NaClBitCodeAbbrevOp &Op1,
241 return Op1.Compare(Op2) != 0;
244 static inline bool operator>=(const NaClBitCodeAbbrevOp &Op1,
246 return Op1.Compare(Op2) >= 0;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp346 const MachineOperand &Op1 = MI->getOperand(1); in profit() local
348 int32_t Prof1 = Op1.isImm() ? profitImm(Op1.getImm()) : 0; in profit()
704 MachineOperand &Op1 = MI->getOperand(1); in splitImmediate() local
705 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
706 uint64_t V = Op1.getImm(); in splitImmediate()
731 MachineOperand &Op1 = MI->getOperand(1); in splitCombine() local
741 if (!Op1.isReg()) { in splitCombine()
743 .add(Op1); in splitCombine()
746 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
761 MachineOperand &Op1 = MI->getOperand(1); in splitExt() local
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/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp659 MachineOperand &Op1 = MI->getOperand(1); in splitImmediate() local
660 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
661 uint64_t V = Op1.getImm(); in splitImmediate()
687 MachineOperand &Op1 = MI->getOperand(1); in splitCombine() local
697 if (Op1.isImm()) { in splitCombine()
699 .addImm(Op1.getImm()); in splitCombine()
700 } else if (Op1.isReg()) { in splitCombine()
702 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
720 MachineOperand &Op1 = MI->getOperand(1); in splitExt() local
721 assert(Op0.isReg() && Op1.isReg()); in splitExt()
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