| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86CmovConversion.cpp | 823 unsigned Op1Reg = MIIt->getOperand(1).getReg(); in convertCmovInstsToBranches() local
830 std::swap(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
832 auto Op1Itr = RegRewriteTable.find(Op1Reg); in convertCmovInstsToBranches()
834 Op1Reg = Op1Itr->second.first; in convertCmovInstsToBranches()
844 .addReg(Op1Reg) in convertCmovInstsToBranches()
853 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
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| D | X86InstructionSelector.cpp | 978 const unsigned Op1Reg = I.getOperand(3).getReg(); in selectUadde() local
1016 .addReg(Op1Reg); in selectUadde()
1466 unsigned Op1Reg = I.getOperand(2).getReg(); in selectShift() local
1470 .addReg(Op1Reg); in selectShift()
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| D | X86FastISel.cpp | 1428 unsigned Op1Reg = getRegForValue(Op1); in X86FastEmitCompare() local
1429 if (Op1Reg == 0) return false; in X86FastEmitCompare()
1432 .addReg(Op1Reg); in X86FastEmitCompare()
1845 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectShift() local
1846 if (Op1Reg == 0) return false; in X86SelectShift()
1848 CReg).addReg(Op1Reg); in X86SelectShift()
1954 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectDivRem() local
1955 if (Op1Reg == 0) in X86SelectDivRem()
1991 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()
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| D | X86ISelLowering.cpp | 27033 unsigned Op1Reg = MIIt->getOperand(1).getReg(); in createPHIsForCMOVsInSinkBB() local
27040 std::swap(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
27042 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end()) in createPHIsForCMOVsInSinkBB()
27043 Op1Reg = RegRewriteTable[Op1Reg].first; in createPHIsForCMOVsInSinkBB()
27049 .addReg(Op1Reg) in createPHIsForCMOVsInSinkBB()
27055 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
27195 unsigned Op1Reg = FirstCMOV.getOperand(1).getReg(); in EmitLoweredCascadedSelect() local
27199 .addReg(Op1Reg) in EmitLoweredCascadedSelect()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 880 unsigned Op1Reg = getRegForValue(Op1); in X86FastEmitCompare() local
881 if (Op1Reg == 0) return false; in X86FastEmitCompare()
884 .addReg(Op1Reg); in X86FastEmitCompare()
1176 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectShift() local
1177 if (Op1Reg == 0) return false; in X86SelectShift()
1179 CReg).addReg(Op1Reg); in X86SelectShift()
1220 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectSelect() local
1221 if (Op1Reg == 0) return false; in X86SelectSelect()
1229 .addReg(Op1Reg).addReg(Op2Reg); in X86SelectSelect()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 264 unsigned Op1Reg, bool Op1IsKill);
268 unsigned Op1Reg, bool Op1IsKill);
272 unsigned Op1Reg, bool Op1IsKill);
3995 unsigned Op1Reg, bool Op1IsKill) { in emitLSL_rr() argument
4010 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSL_rr()
4013 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSL_rr()
4101 unsigned Op1Reg, bool Op1IsKill) { in emitLSR_rr() argument
4117 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSR_rr()
4120 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSR_rr()
4222 unsigned Op1Reg, bool Op1IsKill) { in emitASR_rr() argument
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 218 unsigned Op1Reg, bool Op1IsKill);
222 unsigned Op1Reg, bool Op1IsKill);
226 unsigned Op1Reg, bool Op1IsKill);
3909 unsigned Op1Reg, bool Op1IsKill) { in emitLSL_rr() argument
3924 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSL_rr()
3927 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSL_rr()
4015 unsigned Op1Reg, bool Op1IsKill) { in emitLSR_rr() argument
4031 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSR_rr()
4034 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSR_rr()
4136 unsigned Op1Reg, bool Op1IsKill) { in emitASR_rr() argument
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1620 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in SelectSelect() local
1621 if (Op1Reg == 0) return false; in SelectSelect()
1666 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); in SelectSelect()
1670 .addReg(Op1Reg) in SelectSelect()
1674 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); in SelectSelect()
1677 .addReg(Op1Reg) in SelectSelect()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1636 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in SelectSelect() local
1637 if (Op1Reg == 0) return false; in SelectSelect()
1682 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); in SelectSelect()
1686 .addReg(Op1Reg) in SelectSelect()
1690 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); in SelectSelect()
1693 .addReg(Op1Reg) in SelectSelect()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1399 unsigned Op1Reg = getRegForValue(Op1); in X86FastEmitCompare() local
1400 if (Op1Reg == 0) return false; in X86FastEmitCompare()
1403 .addReg(Op1Reg); in X86FastEmitCompare()
1751 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectShift() local
1752 if (Op1Reg == 0) return false; in X86SelectShift()
1754 CReg).addReg(Op1Reg); in X86SelectShift()
1860 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectDivRem() local
1861 if (Op1Reg == 0) in X86SelectDivRem()
1897 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1757 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in selectShift() local
1758 if (!Op1Reg) in selectShift()
1775 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1402 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in SelectSelect() local
1403 if (Op1Reg == 0) return false; in SelectSelect()
1413 .addReg(Op1Reg).addReg(Op2Reg) in SelectSelect()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1983 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in selectShift() local
1984 if (!Op1Reg) in selectShift()
2001 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
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