| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 636 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders, in ProcessSDDbgValues() argument
654 Orders.push_back(std::make_pair(DVOrder, DbgMI)); in ProcessSDDbgValues()
668 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders, in ProcessSourceNode() argument
674 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); in ProcessSourceNode()
681 Orders.push_back(std::make_pair(Order, (MachineInstr*)0)); in ProcessSourceNode()
685 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos()))); in ProcessSourceNode()
686 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
695 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
736 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen); in EmitSchedule()
743 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, in EmitSchedule()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 704 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSDDbgValues()
720 Orders.push_back({DVOrder, DbgMI}); in ProcessSDDbgValues()
734 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSourceNode()
740 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); in ProcessSourceNode()
751 Orders.push_back({Order, (MachineInstr *)nullptr}); in ProcessSourceNode()
755 Orders.push_back({Order, &*std::prev(IP)}); in ProcessSourceNode()
756 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
804 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
843 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen); in EmitSchedule()
850 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, in EmitSchedule()
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| D | FastISel.cpp | 239 Orders[&I] = Order++; in initialize()
266 OrderMap.Orders.erase(&LocalMI); in sinkLocalValueMaterialization()
273 if (OrderMap.Orders.empty()) in sinkLocalValueMaterialization()
280 auto I = OrderMap.Orders.find(&UseInst); in sinkLocalValueMaterialization()
281 assert(I != OrderMap.Orders.end() && in sinkLocalValueMaterialization()
310 unsigned UseOrder = OrderMap.Orders[&DbgVal]; in sinkLocalValueMaterialization()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 702 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSDDbgValues()
719 Orders.push_back(std::make_pair(DVOrder, DbgMI)); in ProcessSDDbgValues()
733 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, in ProcessSourceNode()
739 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); in ProcessSourceNode()
749 Orders.push_back(std::make_pair(Order, (MachineInstr*)nullptr)); in ProcessSourceNode()
753 Orders.push_back(std::make_pair(Order, &*std::prev(Emitter.getInsertPos()))); in ProcessSourceNode()
754 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
802 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
842 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen); in EmitSchedule()
849 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, in EmitSchedule()
[all …]
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 279 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
283 Orders[0].push_back((*Elements)[i]); in CodeGenRegisterClass()
291 Orders[1 + i].append(Order.begin(), Order.end()); in CodeGenRegisterClass()
368 Orders.resize(Super.Orders.size()); in inheritProperties()
369 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) in inheritProperties()
370 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) in inheritProperties()
371 if (contains(RegBank.getReg(Super.Orders[i][j]))) in inheritProperties()
372 Orders[i].push_back(Super.Orders[i][j]); in inheritProperties()
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| D | CodeGenRegisters.h | 91 std::vector<SmallVector<Record*, 16> > Orders; variable
176 return Orders[No];
180 unsigned getNumOrders() const { return Orders.size(); } in getNumOrders()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| D | ConstantHoisting.cpp | 233 SmallVector<BasicBlock *, 16> Orders; in findBestInsertionSet() local
234 Orders.push_back(Entry); in findBestInsertionSet()
235 while (Idx != Orders.size()) { in findBestInsertionSet()
236 BasicBlock *Node = Orders[Idx++]; in findBestInsertionSet()
239 Orders.push_back(ChildDomNode->getBlock()); in findBestInsertionSet()
250 InsertPtsMap.reserve(Orders.size() + 1); in findBestInsertionSet()
251 for (auto RIt = Orders.rbegin(); RIt != Orders.rend(); RIt++) { in findBestInsertionSet()
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| /external/llvm/lib/CodeGen/ |
| D | InlineSpiller.cpp | 99 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1142 SmallVectorImpl<MachineDomTreeNode *> &Orders, in getVisitOrders() argument
1201 Orders.push_back(MDT.DT->getNode(Root)); in getVisitOrders()
1203 MachineDomTreeNode *Node = Orders[idx++]; in getVisitOrders()
1209 Orders.push_back(Child); in getVisitOrders()
1211 } while (idx != Orders.size()); in getVisitOrders()
1212 assert(Orders.size() == WorkSet.size() && in getVisitOrders()
1216 DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n"); in getVisitOrders()
1217 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin(); in getVisitOrders()
1218 for (; RIt != Orders.rend(); RIt++) in getVisitOrders()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | InlineSpiller.cpp | 125 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1198 SmallVectorImpl<MachineDomTreeNode *> &Orders, in getVisitOrders() argument
1257 Orders.push_back(MDT.getBase().getNode(Root)); in getVisitOrders()
1259 MachineDomTreeNode *Node = Orders[idx++]; in getVisitOrders()
1265 Orders.push_back(Child); in getVisitOrders()
1267 } while (idx != Orders.size()); in getVisitOrders()
1268 assert(Orders.size() == WorkSet.size() && in getVisitOrders()
1272 LLVM_DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n"); in getVisitOrders()
1273 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin(); in getVisitOrders()
1274 for (; RIt != Orders.rend(); RIt++) in getVisitOrders()
[all …]
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 269 std::vector<SmallVector<Record*, 16> > Orders; variable
384 return Orders[No];
388 unsigned getNumOrders() const { return Orders.size(); } in getNumOrders()
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| D | CodeGenRegisters.cpp | 678 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
682 Orders[0].push_back((*Elements)[i]); in CodeGenRegisterClass()
693 Orders[1 + i].append(Order.begin(), Order.end()); in CodeGenRegisterClass()
757 Orders.resize(Super.Orders.size()); in inheritProperties()
758 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) in inheritProperties()
759 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) in inheritProperties()
760 if (contains(RegBank.getReg(Super.Orders[i][j]))) in inheritProperties()
761 Orders[i].push_back(Super.Orders[i][j]); in inheritProperties()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 295 std::vector<SmallVector<Record*, 16>> Orders; variable
423 return Orders[No];
427 unsigned getNumOrders() const { return Orders.size(); } in getNumOrders()
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| D | CodeGenRegisters.cpp | 751 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
756 Orders[0].push_back((*Elements)[i]); in CodeGenRegisterClass()
768 Orders[1 + i].append(Order.begin(), Order.end()); in CodeGenRegisterClass()
844 Orders.resize(Super.Orders.size()); in inheritProperties()
845 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) in inheritProperties()
846 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) in inheritProperties()
847 if (contains(RegBank.getReg(Super.Orders[i][j]))) in inheritProperties()
848 Orders[i].push_back(Super.Orders[i][j]); in inheritProperties()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/X86/ |
| D | dbg-value-transfer-order.ll | 24 ; with the Orders insertion point vector.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 572 DenseMap<MachineInstr *, unsigned> Orders; member
|
| /external/tensorflow/tensorflow/core/util/sparse/ |
| D | README.md | 192 conc_order = {1, 0} // Orders match along all inputs
|
| /external/libtextclassifier/actions/ |
| D | actions_model.fbs | 128 // Orders of charactergrams to extract, e.g. 2 means character bigrams, 3
|
| /external/libtextclassifier/annotator/ |
| D | model.fbs | 523 // Orders of charactergrams to extract. E.g., 2 means character bigrams, 3
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 1450 llvm::AtomicOrdering Orders[5] = { in EmitBuiltinExpr() local
1464 Ptr, NewVal, Orders[i]); in EmitBuiltinExpr()
1516 llvm::AtomicOrdering Orders[3] = { in EmitBuiltinExpr() local
1526 Store->setOrdering(Orders[i]); in EmitBuiltinExpr()
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| /external/cldr/tools/java/org/unicode/cldr/util/data/ |
| D | europe | 386 # Summer Time Act, 1925 and Summer Time Orders, 1926 and 1947:
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| /external/brotli/tests/testdata/ |
| D | plrabn12.txt | 807 Each in his Hierarchy, the Orders bright.
8653 To those bright Orders uttered thus his voice.
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