| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 396 RECIP_S = 13, enumerator
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| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 429 RECIP_S = 13, enumerator
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| /external/v8/src/mips/ |
| D | constants-mips.h | 616 RECIP_S = ((2U << 3) + 5), enumerator
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| D | assembler-mips.cc | 2888 GenInstrRegister(COP1, S, f0, fs, fd, RECIP_S); in recip_s()
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| D | simulator-mips.cc | 3260 case RECIP_S: in DecodeTypeRegisterSRsType()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 647 RECIP_S = ((2U << 3) + 5), enumerator
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| D | assembler-mips64.cc | 3280 GenInstrRegister(COP1, S, f0, fs, fd, RECIP_S); in recip_s()
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| D | simulator-mips64.cc | 2713 case RECIP_S: in DecodeTypeRegisterSRsType()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 456 def : InstRW<[P5600WriteFPURsqrtS], (instrs RECIP_S, RSQRT_S)>;
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| D | MipsInstrFPU.td | 376 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 901 {DBGFIELD("RECIP_S") 1, false, false, 30, 2, 12, 1, 0, 0}, // #626
1921 {DBGFIELD("RECIP_S") 1, false, false, 63, 3, 16, 1, 0, 0}, // #626
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| D | MipsGenMCCodeEmitter.inc | 2161 UINT64_C(1174405141), // RECIP_S
3181 case Mips::RECIP_S:
9887 …nc | Feature_HasMips4_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // RECIP_S = 2148
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| D | MipsGenInstrInfo.inc | 2163 RECIP_S = 2148,
3283 RECIP_S = 626,
6208 … 2, 1, 4, 626, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2148 = RECIP_S
10218 { Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM },
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| D | MipsGenAsmWriter.inc | 3376 23619U, // RECIP_S
6007 0U, // RECIP_S
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| D | MipsGenDisassemblerTables.inc | 3368 /* 2933 */ MCD::OPC_Decode, 228, 16, 205, 1, // Opcode: RECIP_S
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| D | MipsGenAsmMatcher.inc | 7057 …{ 7655 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Fe…
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