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Searched refs:Sched (Results 1 – 25 of 130) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepTimingClasses.h23 case Hexagon::Sched::tc_16d0d8d5: in is_TC3x()
24 case Hexagon::Sched::tc_1853ea6d: in is_TC3x()
25 case Hexagon::Sched::tc_60571023: in is_TC3x()
26 case Hexagon::Sched::tc_7934b9df: in is_TC3x()
27 case Hexagon::Sched::tc_8fd5f294: in is_TC3x()
28 case Hexagon::Sched::tc_b9c0b731: in is_TC3x()
29 case Hexagon::Sched::tc_bcc96cee: in is_TC3x()
30 case Hexagon::Sched::tc_c6ce9b3f: in is_TC3x()
31 case Hexagon::Sched::tc_c6ebf8dd: in is_TC3x()
32 case Hexagon::Sched::tc_c82dc1ff: in is_TC3x()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
97 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
98 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
103 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
104 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
105 case PPC::Sched::IIC_LdStLWA: in mustComeFirst()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
97 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
98 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
103 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
104 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
105 case PPC::Sched::IIC_LdStLWA: in mustComeFirst()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrExtension.td17 "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>;
20 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
24 "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
27 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
32 "{cltq|cdqe}", []>, Sched<[WriteALU]>;
36 "{cqto|cqo}", []>, Sched<[WriteALU]>;
43 TB, OpSize16, Sched<[WriteALU]>;
47 TB, OpSize16, Sched<[WriteALULd]>;
52 OpSize32, Sched<[WriteALU]>;
56 OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrXOP.td17 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[SchedWritePHAdd.XMM]>;
21 Sched<[SchedWritePHAdd.XMM.Folded, ReadAfterLd]>;
48 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
52 Sched<[sched.Folded, ReadAfterLd]>;
59 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
63 Sched<[sched.Folded, ReadAfterLd]>;
70 [(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L, Sched<[sched]>;
74 Sched<[sched.Folded, ReadAfterLd]>;
102 XOP, Sched<[sched]>;
109 XOP_4V, VEX_W, Sched<[sched.Folded, ReadAfterLd]>;
[all …]
DX86InstrControl.td125 OpSize16, Sched<[WriteJump]>;
128 OpSize16, Sched<[WriteJumpLd]>;
132 OpSize32, Sched<[WriteJump]>;
135 OpSize32, Sched<[WriteJumpLd]>;
139 Sched<[WriteJump]>;
142 Sched<[WriteJumpLd]>;
148 OpSize16, Sched<[WriteJump]>, NOTRACK;
152 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>,
157 OpSize32, Sched<[WriteJump]>, NOTRACK;
160 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>,
[all …]
DX86InstrMMX.td42 Sched<[sched]> {
50 Sched<[sched.Folded, ReadAfterLd]>;
61 Sched<[sched]>;
67 Sched<[sched.Folded, ReadAfterLd]>;
72 Sched<[schedImm]>;
82 Sched<[sched]>;
88 Sched<[sched.Folded]>;
101 Sched<[sched]>;
108 Sched<[sched.Folded, ReadAfterLd]>;
119 Sched<[sched]>;
[all …]
DX86InstrSSE.td31 Sched<[sched]>;
38 Sched<[sched.Folded, ReadAfterLd]>;
53 Sched<[sched]>;
60 Sched<[sched.Folded, ReadAfterLd]>;
76 Sched<[sched]>;
84 Sched<[sched.Folded, ReadAfterLd]>;
99 Sched<[sched]>;
106 Sched<[sched.Folded, ReadAfterLd]>;
182 Sched<[SchedWriteFShuffle.XMM]>;
189 Sched<[SchedWriteFShuffle.XMM]>, FoldGenData<Name#rr>;
[all …]
DX86InstrFMA.td45 Sched<[sched]>;
54 Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>;
65 []>, Sched<[sched]>;
74 Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>;
85 []>, Sched<[sched]>;
96 Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>;
186 Sched<[sched]>;
195 Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>;
206 []>, Sched<[sched]>;
215 Sched<[sched.Folded, ReadAfterLd, ReadAfterLd]>;
[all …]
DX86InstrArithmetic.td49 class SchedLoadReg<SchedWrite SW> : Sched<[SW,
66 (implicit EFLAGS)]>, Sched<[WriteIMul]>;
71 []>, OpSize16, Sched<[WriteIMul]>;
77 OpSize32, Sched<[WriteIMul]>;
83 Sched<[WriteIMul64]>;
113 Sched<[WriteIMul]>;
117 OpSize16, Sched<[WriteIMul]>;
121 OpSize32, Sched<[WriteIMul]>;
125 Sched<[WriteIMul64]>;
159 Sched<[WriteIMul]>, TB, OpSize16;
[all …]
DX86InstrAVX512.td514 AVX512AIi8Base, EVEX_4V, Sched<[sched]>;
527 Sched<[sched.Folded, ReadAfterLd]>;
778 EVEX_4V, Sched<[SchedWriteFShuffle.XMM]>;
786 Sched<[SchedWriteFShuffle.XMM.Folded, ReadAfterLd]>;
808 AVX512AIi8Base, EVEX, Sched<[SchedRR]>;
817 Sched<[SchedMR]>;
826 EVEX_K, EVEX, Sched<[SchedMR]>, NotMemoryFoldable;
1107 EVEX, VEX_WIG, Sched<[WriteVecExtract]>;
1114 EVEX, VEX_WIG, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecExtractSt]>;
1160 T8PD, EVEX, Sched<[SchedRR]>;
[all …]
DX86InstrCMovSetCC.td17 multiclass CMOV<bits<8> opc, string Mnemonic, X86FoldableSchedWrite Sched,
20 isCommutable = 1, SchedRW = [Sched] in {
41 SchedRW = [Sched.Folded, ReadAfterLd] in {
86 TB, Sched<[WriteSETCC]>;
90 TB, Sched<[WriteSETCCStore]>;
/external/llvm/lib/Target/X86/
DX86InstrExtension.td45 TB, OpSize16, Sched<[WriteALU]>;
49 TB, OpSize16, Sched<[WriteALULd]>;
54 OpSize32, Sched<[WriteALU]>;
58 OpSize32, Sched<[WriteALULd]>;
62 OpSize32, Sched<[WriteALU]>;
66 OpSize32, TB, Sched<[WriteALULd]>;
71 TB, OpSize16, Sched<[WriteALU]>;
75 TB, OpSize16, Sched<[WriteALULd]>;
80 OpSize32, Sched<[WriteALU]>;
84 OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrMMX.td23 let Sched = WriteVecALU in {
41 let Sched = WriteVecLogic in
46 let Sched = WriteVecIMul in
51 let Sched = WriteVecIMul in {
65 let Sched = WriteShuffle in {
81 } // Sched
83 let Sched = WriteCvtF2I in {
102 Sched<[itins.Sched]> {
110 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
120 Sched<[WriteVecShift]>;
[all …]
DX86InstrControl.td137 OpSize16, Sched<[WriteJump]>;
140 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
144 OpSize32, Sched<[WriteJump]>;
147 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>;
151 Sched<[WriteJump]>;
154 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
160 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
164 IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
168 Sched<[WriteJump]>;
172 Sched<[WriteJumpLd]>;
[all …]
DX86InstrSSE.td20 X86FoldableSchedWrite Sched = WriteFAdd;
38 let Sched = WriteFAdd in {
52 let Sched = WriteFMul in {
66 let Sched = WriteFDiv in {
81 let Sched = WriteFAdd in {
95 let Sched = WriteFMul in {
109 let Sched = WriteFDiv in {
123 let Sched = WriteVecLogic in
132 let Sched = WriteVecALU in {
142 let Sched = WriteVecIMul in
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb.td376 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
389 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
409 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
420 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
441 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
453 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
469 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
478 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
488 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
493 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
[all …]
DARMInstrVFP.td340 Sched<[WriteFPALU64]>;
347 Sched<[WriteFPALU32]> {
358 Sched<[WriteFPALU32]>;
365 Sched<[WriteFPALU64]>;
372 Sched<[WriteFPALU32]>{
383 Sched<[WriteFPALU32]>;
390 Sched<[WriteFPDIV64]>;
397 Sched<[WriteFPDIV32]>;
404 Sched<[WriteFPDIV32]>;
411 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>;
[all …]
DARMInstrNEON.td667 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD1]> {
675 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD2]> {
696 "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
704 "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
713 "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> {
721 "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> {
740 "$Vd, $Rn", "", []>, Sched<[WriteVLD3]> {
749 "$Rn.addr = $wb", []>, Sched<[WriteVLD3]> {
757 "$Rn.addr = $wb", []>, Sched<[WriteVLD3]> {
773 def VLD1d8TPseudo : VLDQQPseudo<IIC_VLD1x3>, Sched<[WriteVLD3]>;
[all …]
DARMInstrInfo.td1364 Sched<[WriteALU, ReadALU]> {
1377 Sched<[WriteALU, ReadALU, ReadALU]> {
1393 Sched<[WriteALUsi, ReadALU]> {
1409 Sched<[WriteALUsr, ReadALUsr]> {
1437 Sched<[WriteALU, ReadALU]> {
1450 Sched<[WriteALU, ReadALU, ReadALU]> {
1465 Sched<[WriteALUsi, ReadALU]> {
1481 Sched<[WriteALUsr, ReadALUsr]> {
1507 Sched<[WriteALU, ReadALU]>;
1512 Sched<[WriteALU, ReadALU, ReadALU]> {
[all …]
DARMInstrThumb2.td545 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]> {
564 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
592 Sched<[WriteALU, ReadALU]> {
602 Sched<[WriteALU, ReadALU, ReadALU]> {
616 Sched<[WriteALUsi, ReadALU]> {
676 Sched<[WriteALU, ReadALU]> {
687 Sched<[WriteALU, ReadALU, ReadALU]> {
700 Sched<[WriteALUsi, ReadALU]> {
722 Sched<[WriteALU, ReadALU]>;
728 Sched<[WriteALU, ReadALU, ReadALU]> {
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td359 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
372 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
392 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
403 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
424 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
436 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
452 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
461 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
471 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
476 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DSVEInstrFormats.td246 []>, Sched<[]> {
292 []>, Sched<[]> {
308 []>, Sched<[]> {
329 []>, Sched<[]> {
366 []>, Sched<[]> {
411 []>, Sched<[]> {
439 []>, Sched<[]> {
469 []>, Sched<[]> {
496 []>, Sched<[]> {
528 []>, Sched<[]> {
[all …]
/external/perfetto/test/trace_processor/
Dindex17 # Sched
20 # Sched reason
25 # Sched wakeup
85 # Sched table
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
DDispatchStage.h88 RegisterFile &F, Scheduler &Sched) in DispatchStage() argument
90 CarryOver(0U), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {} in DispatchStage()

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